A breakpoint is set using a pair of registers:
a Breakpoint Value Register (BVR)
a Breakpoint Control Register (BCR).
There are six BVRs, BVR0 to BRV5, and six BCRs, BCR0 to BCR5. Together, a BVR and the corresponding BCR make a Breakpoint Register Pair (BRP). So, for example, BVR2 and BCR2 together make up BRP2.
In a similar way, a watchpoint is set using a pair of registers:
a Watchpoint Value Register (WVR)
a Watchpoint Control Register (WCR).
There are two WVRs, WVR0 and WRV1, and two WCRs, WCR0 and WCR1. Together, a WVR and the corresponding WCR make a Watchpoint Register Pair (WRP). So, for example, WVR0 and WCR0 together make up WRP0.
Normally, the contents of a BVR are compared with the IVA bus. However, two of the BVPs are Context ID capable, meaning that the BVR contents can be compared with the CP15 Context ID Register, c13, instead of with the IVA bus. For these BVPs, values in the BCR control whether the BVR is compared with the Context ID Register or with the IVA bus.
Table 13.14 summarizes the breakpoint and watchpoint registers that are implemented in the ARM1136JF-S processor.
|Binary address||Register number||CP14 debug register name||Abbreviation||Context ID capable?|
|b100||b0000-b0011||c64-c67||Breakpoint Value Registers 0-3||BVR0-3||No|
|b0100-b0101||c68-c69||Breakpoint Value Registers 4-5||BVR4-5||Yes|
|b101||b0000-b0011||c80-c83||Breakpoint Control Registers 0-3||BCR0-3||No|
|b0100-b0101||c84-c85||Breakpoint Control Registers 4-5||BCR4-5||Yes|
|b110||b0000-b0001||c96-c97||Watchpoint Value Registers 0-1||WVR0-1||-|
|b111||b0000-b0001||c112-c113||Watchpoint Control Registers 0-1||WCR0-1||-|