The problem with Data Cache writes is that, while debugging,
you might want to write some instructions to memory, either some
code to be debugged or a
BKPT instruction. This poses
coherency issues on the Instruction Cache.
In ARM1136JF-S systems, CP15 c15, the Cache Debug Control Register, enables you to use the following features:
You can put the processor in a state where data writes work as if the cache is enabled and every region of memory is Write-Through. This facility is accessible from both the core and the DBGTAP debugger side. See c15, Cache Debug Control Register.
ARMv6 architecture provides CP15 instructions for invalidating the Instruction Cache, described in c7, Cache Operations Register to ensure that, after a write, there are no out-of-date words in the Instruction Cache.