The following external signals are used by debug:
Debug acknowledge signal. The processor asserts this output signal to indicate the system has entered Debug state. See Debug state for a definition of the Debug state.
Debug enable signal. When this signal is LOW, DSCR[15:14] is read as 0 and the processor cannot enter Debug state.
External debug request signal. As described in External debug request signal, this input signal forces the processor into Debug state.
Powerdown disable signal generated from DSCR. When this signal is HIGH, the system power controller is forced into Emulate mode. This is to avoid losing CP14 Debug state that can only be written through the DBGTAP. Therefore, DSCR must only be set if Halting debug-mode debugging is necessary.