The ARM1136JF-S MMU works with the cache memory system to control accesses to and from external memory. The MMU also controls the translation of Virtual Addresses to physical addresses.
The ARM1136JF-S processor implements an ARMv6 MMU to provide address translation and access permission checks for the instruction and data ports of the ARM1136JF-S processor. The MMU controls table-walking hardware that accesses translation tables in main memory. A single set of two-level page tables stored in main memory controls the contents of the instruction and data side Translation Lookaside Buffers (TLBs). The finished Virtual Address to physical address translation is put into the TLB. The TLBs are enabled from a single bit in CP15 Control Register c1, providing a single address translation and protection scheme from software.
The MMU features are:
Standard ARMv6 MMU mapping sizes, domains, and access protection scheme.
Mapping sizes are 4KB, 64KB, 1MB, and 16MB.
You specify access permissions for 1MB sections and 16MB supersections for the entire section.
You can specify access permissions for 64KB large pages and 4KB small pages separately for each quarter of the page. These quarters are called subpages.
One 2-way associative unified TLB with a total of 64 entries, organized as 2 x 32 entries, and an additional lockdown region with eight entries.
You can mark entries as a global mapping, or associated with a specific Address Space Identifier (ASID) to eliminate the requirement for TLB flushes on most context switches.
Access permissions are extended to enable supervisor read-only and supervisor/user read-only modes to be simultaneously supported
Memory region attributes to mark pages shared by multiple processors.
Hardware page table walks.
Round-robin replacement algorithm.
The MMU memory system architecture enables fine-grained control of a memory system. This is controlled by a set of virtual to physical address mappings and associated memory properties held within one or more structures known as TLBs within the MMU. The contents of the TLBs are managed through hardware translation lookups from a set of translation tables in memory.
To prevent requiring a TLB invalidation on a context switch, you can mark each virtual to physical address mapping as being associated with a particular address space, or as global for all address spaces. Only global mappings and those for the current address space are enabled at any time. By changing the Address Space IDentifier (ASID) you can alter the enabled set of virtual to physical address mappings. The set of memory properties associated with each TLB entry include:
- Memory access permission control
This controls if a program has no-access, read-only access, or read/write access to the memory area. When an access is attempted without the required permission, a memory abort is signaled to the processor. The level of access possible can also be affected by whether the program is running in User mode, or a privileged mode, and by the use of domains. See Memory access control for more details.
- Memory region attributes
These describe properties of a memory region. Examples include Device, Noncacheable, Write-Through, and Write-Back. If an entry for a Virtual Address is not found in a TLB then a set of translation tables in memory are automatically searched by hardware to create a TLB entry. This process is known as a translation table walk. If the ARM1136JF-S processor is in ARMv5 backwards-compatible mode some new features, such as ASIDs, are not available. The MMU architecture also enables specific TLB entries to be locked down in a TLB. This ensures that accesses to the associated memory areas never require looking up by a translation table walk. This minimizes the worst-case access time to code and data for real-time routines.