When the CP15 Control Register c1 Bit 23 is set to 1, the subpage AP bits are disabled and the page tables have support for ARMv6 MMU features. Four new page table bits are added to support these features:
The Not-Global (nG) bit, determines if the translation is marked as global (0), or process-specific (1) in the TLB. For process-specific translations the translation is inserted into the TLB using the current ASID, from the ContextID Register, CP15 c13.
The Shared (S) bit, determines if the translation is for Non-Shared (0), or Shared (1) memory. This only applies to Normal memory regions. Device memory can be Shared or Non-Shared as determined by the TEX bits and the C and B bits.
The Execute-Never (XN) bit, determines if the region is Executable (0) or Not-executable (1).
Three access permission bits. The access permissions extension (APX) bit, provides an extra access permission bit.
All ARMv6 page table mappings support the TEX field.
Figure 6.7 shows the format of an ARMv6 first-level descriptor when subpages are enabled.
Figure 6.8 shows the format of an ARMv6 first-level descriptor when subpages are disabled.
In addition to the invalid translation, bits [1:0] = b00, translations for the reserved entry, bits [1:0] = b11, result in a translation fault.
Bit 18 of the first-level descriptor selects between a 1MB section and a 16MB supersection. For details of supersections see Supersections.
Figure 6.9 shows the format of an ARMv6 second-level descriptor.
Figure 6.10 shows an overview of the section, supersection, and page translation process using ARMv6 descriptors.