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6.3. Memory access sequence

When the ARM1136JF-S processor generates a memory access, the MMU:

  1. Performs a lookup for a mapping for the requested Virtual Address and current ASID in the relevant Instruction or Data MicroTLB.

  2. If step 1 misses then a lookup for a mapping for the requested Virtual Address and current ASID in the Main TLB is performed.

If no global mapping, or mapping for the currently selected ASID, for the Virtual Address can be found in the TLBs then a translation table walk is automatically performed by hardware. See Hardware page table translation.

If a matching TLB entry is found then the information it contains is used as follows:

  1. The access permission bits and the domain are used to determine the access privileges for the attempted access. If the privileges are valid the access is enabled to proceed. Otherwise the MMU signals a memory abort. Memory access control describes how this is done.

  2. The memory region attributes are used to control the Cache and Write Buffer, and to determine if the access is cached, uncached, or Device, and if it is Shared, as described in Memory region attributes.

  3. The physical address is used for any access to external or tightly coupled memory to perform Tag matching for cache entries.