The ARM1136JF-S processor provides a set of memory attributes that have characteristics that are suited to particular devices, including memory devices, that can be contained in the memory map. The ordering of accesses for regions of memory is also defined by the memory attributes. There are three mutually exclusive main memory type attributes:
These are used to describe the memory regions. The marking of the same memory locations as having two different attributes in the MMU, for example using synonyms in a virtual to physical address mapping, results in Unpredictable behavior.
A summary of the memory attributes is shown in Table 6.10.
|Memory type||Shared/ Non-Shared||Other attributes||Description|
All memory accesses to Strongly Ordered memory occur in program order.
Some backwards compatibility constraints exist with ARMv5 instructions that change the CPSR interrupt masks (see Strongly Ordered memory attribute).
All Strongly Ordered accesses are assumed to be shared.
|Device||Shared||-||Designed to handle memory-mapped peripherals that are shared by several processors.|
|Non-Shared||-||Designed to handle memory-mapped peripherals that are used only by a single processor.|
|Normal||Shared||Noncacheable/ Write-Through Cacheable/ Write-Back Cacheable||Designed to handle normal memory that is shared between several processors.|
|Non-Shared||Noncacheable/ Write-Through Cacheable/ Write-Back Cacheable||Designed to handle normal memory that is used only by a single processor.|