Mechanisms that can cause the ARM1136JF-S processor to take an exception because of a memory access are:
- MMU fault
The MMU detects a restriction and signals the processor.
- Debug abort
Monitor debug-mode debug is enabled and a breakpoint or a watchpoint has been detected.
- External abort
The external memory system signals an illegal or faulting memory access.
Collectively these are called aborts. Accesses that cause aborts are said to be aborted. If the memory request that aborts is an instruction fetch, then a Prefetch Abort exception is raised if and when the processor attempts to execute the instruction corresponding to the aborted access.
If the aborted access is a data access or a cache maintenance operation, a Data Abort exception is raised.
All Data Aborts, and aborts caused by cache maintenance operations, cause the Data Fault Status Register (DFSR) to be updated so that you can determine the cause of the abort.
For all aborts, excluding External Aborts, other than on translation, the Fault Address Register (FAR) is updated with the address that caused the abort. External Data Aborts, other than on translation, can all be imprecise and therefore the FAR does not contain the address of the abort. See Imprecise Data Abort mask in the CPSR/SPSR for more details on imprecise Data Aborts.
For instruction aborts the value of R14 is used by the abort handler to determine the address that caused the abort.