The MMU is controlled by the system control coprocessor (CP15) registers, shown in Table 6.18, in conjunction with page table descriptors stored in memory.
You can access all the registers with instructions of the form:
MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
MCR p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
Where CRn is the system control coprocessor register. Unless specified otherwise, CRm and Opcode_2 Should Be Zero.
Reference to description
|TLB Type Register||See c0, TLB Type Register|
Translation Table Base Register 0
Translation Table Base Register 1
Translation Table Base Control Register
Domain Access Control Register
Data Fault Status Register (DFSR)
Instruction Fault Status Register (IFSR)
Fault Address Register (FAR)
Watchpoint Fault Address Register (WFAR)
Cache Operations Register
TLB Operations Register
|TLB Lockdown Register||See c10, TLB Lockdown Register|
|Primary Region Remap Register||See Primary Region Remap Register (PRRR)|
|Normal Memory Remap Register||See Normal Memory Remap Register (NMRR)|
FCSE PID Register
|User Read/Write Thread and Process ID Register||See c13, Thread and process ID registers|
|User Read-only Thread and Process ID Register||See c13, Thread and process ID registers|
|Privileged Only Thread and Process ID Register||See c13, Thread and process ID registers|
All the CP15 MMU registers, except CP15 c7 and CP15 c8, contain
state that you read using
MRC instructions and written
MCR instructions. Registers c5 and c6 are
also written by the MMU. Reading CP15 c7 and c8 is Unpredictable.
See the register descriptions for more information.