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Using this manual

This manual is organized into the following chapters:

Chapter 1 Introduction

Read this chapter for an introduction to the ARM1136JF-S processor and descriptions of the major functional blocks.

Chapter 2 Programmer’s Model

Read this chapter for a description of the ARM1136JF-S registers and programming details.

Chapter 3 System Control Coprocessor

Read this chapter for a description of the ARM1136JF-S control coprocessor CP15 registers and programming details.

Chapter 4 Unaligned and Mixed-Endian Data Access Support

Read this chapter for a description of the ARM1136JF-S processor support for unaligned and mixed-endian data accesses.

Chapter 5 Program Flow Prediction

Read this chapter for a description of the functions of the ARM1136JF-S Prefetch Unit, including static and dynamic branch prediction and the return stack.

Chapter 6 Memory Management Unit

Read this chapter for a description of the ARM1136JF-S Memory Management Unit (MMU) and the address translation process.

Chapter 7 Level One Memory System

Read this chapter for a description of the ARM1136JF-S level one memory system, including caches, TCM, DMA, SmartCache, TLBs, and Write Buffer.

Chapter 8 Level Two Interface

Read this chapter for a description of the ARM1136JF-S level two memory interface and the peripheral port.

Chapter 9 Clocking and Resets

Read this chapter for a description of the ARM1136JF-S clocking modes and the reset signals.

Chapter 10 Power Control

Read this chapter for a description of the ARM1136JF-S power control facilities.

Chapter 11 Coprocessor Interface

Read this chapter for details of the ARM1136JF-S coprocessor interface.

Chapter 12 Vectored Interrupt Controller Port

Read this chapter for a description of the ARM1136JF-S Vectored Interrupt Controller interface.

Chapter 13 Debug

Read this chapter for a description of the ARM1136JF-S debug support.

Chapter 14 Debug Test Access Port

Read this chapter for a description of the JTAG-based ARM1136JF-S Debug Test Access Port.

Chapter 15 Trace Interface Port

Read this chapter for a description of the trace interface port.

Chapter 16 Cycle Timings and Interlock Behavior

Read this chapter for a description of the ARM1136JF-S instruction cycle timing and for details of the interlocks.

Chapter 17 AC Characteristics

Read this chapter for a description of the timing parameters applicable to the ARM1136JF-S processor.

Appendix A Signal Descriptions

Read this appendix for a description of the ARM1136JF-S signals.

Appendix B Functional changes in the rev1 (r1pn) releases

Read this appendix for a description of the changes made in the rev1 release of the ARM1136JF-S and ARM1136J-S processors.

Appendix C Revisions

Read this appendix for a description of the changes specific to this issue of the book.

Glossary

Read the Glossary for definitions of terms used in this manual.

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