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3.3.5. c0, Core feature ID registers

The section describes the core feature ID registers. These registers were added in the r1p0 release. They are all read-only registers, which can only be accessed in privileged mode. The registers are described in the following sections:

c0, Processor Feature Register 0

The purpose of the Processor Feature Register 0 is to provide information about the execution state support and programmer’s model for the processor.

Processor Feature Register 0 is:

  • in CP15 c0

  • a 32-bit read-only register

  • accessible in privileged mode only

  • only available from the rev1 (r1p0) release of the ARM1136JF-S processor.

Figure 3.14 shows the bit arrangement for Processor Feature Register 0.

Figure 3.14. Processor Feature Register 0 format

Figure 3.14. Processor Feature Register 0 format

Table 3.18 lists the bit functions of the Processor Feature Register 0.

Table 3.18. Processor Feature Register 0 bit functions
Bit rangeField nameFunction
[31:28]-

Reserved. RAZ.

[27:24]-

Reserved. RAZ.

[23:20]-

Reserved. RAZ.

[19:16]-

Reserved. RAZ.

[15:12]State3

Indicates support for ThumbEE instruction set.

0x0, ARM1136JF-S processors do not support ThumbEE.

[11:8]State2

Indicates support for Jazelle extension interface.

0x1, ARM1136JF-S processors support Jazelle.

[7:4]State1

Indicates type of Thumb encoding that the processor supports.

0x1, ARM1136JF-S processors support Thumb without the Thumb-2 technology extensions.

[3:0]State0

Indicates support for 32-bit ARM instruction set.

0x1, ARM1136JF-S processors support 32-bit ARM instructions.


Accessing the Processor Feature Register 0

Table 3.19 shows the results of attempted accesses to the Processor Feature Register 0 for each mode.

Table 3.19. Results of accesses to the Processor Feature Register 0
Privileged readPrivileged writeUser read or write
Data readUndefined Instruction exceptionUndefined Instruction exception

To access the Processor Feature Register 0 you read CP15 with:

  • Opcode_1 set to 0

  • CRn set to c0

  • CRm set to c1

  • Opcode_2 set to 0.

For example:

MRC p15, 0, <Rd>, c0, c1, 0               ; Read Processor Feature Register 0

c0, Processor Feature Register 1

The purpose of the Processor Feature Register 1 is to provide information about the execution state support and programmer’s model for the processor.

Processor Feature Register 1 is:

  • in CP15 c0

  • a 32-bit read-only register

  • accessible in privileged mode only

  • only available from the rev1 (r1p0) release of the ARM1136JF-S processor.

Figure 3.15 shows the bit arrangement for Processor Feature Register 1.

Figure 3.15. Processor Feature Register 1 format

Figure 3.15. Processor Feature Register 1 format

Table 3.20 lists the bit functions of the Processor Feature Register 1.

Table 3.20. Processor Feature Register 1 bit functions
Bit rangeField nameFunction
[31:12]-

Reserved. RAZ.

[11:8]Microcontroller programmer’s model

Indicates support for the ARM microcontroller programmer’s model.

0x0, Not supported by ARM1136JF-S processors.

[7:4]Security extension

Indicates support for Security Extensions Architecture v1.

0x0, ARM1136JF-S processors do not support Security Extensions Architecture v1.

[3:0]Programmer’s model

Indicates support for standard ARMv4 programmer’s model.

0x1, ARM1136JF-S processors support the ARMv4 model.


Accessing the Processor Feature Register 1

Table 3.21 shows the results of attempted accesses to the Processor Feature Register 1 for each mode.

Table 3.21. Results of accesses to the Processor Feature Register 1
Privileged readPrivileged writeUser read or write
Data readUndefined Instruction exceptionUndefined Instruction exception

To access the Processor Feature Register 1 you read CP15 with:

  • Opcode_1 set to 0

  • CRn set to c0

  • CRm set to c1

  • Opcode_2 set to 1.

For example:

MRC p15, 0, <Rd>, c0, c1, 1               ; Read Processor Feature Register 1

c0, Debug Feature Register 0

The purpose of the Debug Feature Register 0 is to provide information about the debug system for the processor.

Debug Feature Register 0 is:

  • in CP15 c0

  • a 32-bit read-only register

  • accessible in privileged mode only

  • only available from the rev1 (r1p0) release of the ARM1136JF-S processor.

Figure 3.16 shows the bit arrangement for Debug Feature Register 0.

Figure 3.16. Debug Feature Register 0 format

Figure 3.16. Debug Feature Register 0 format

Table 3.22 lists the bit functions of the Debug Feature Register 0.

Table 3.22. Debug Feature Register 0 bit functions
Bit rangeField nameFunction
[31:28]-

Reserved. RAZ.

[27:24]-

Reserved. RAZ.

[23:20]-

Indicates the type of memory-mapped microcontroller debug model that the processor supports.

0x0, ARM1136JF-S processors do not support this debug model.

[19:16]-

Indicates the type of memory-mapped Trace debug model that the processor supports.

0x0, ARM1136JF-S processors do not support this debug model.

[15:12]-

Indicates the type of coprocessor-based Trace debug model that the processor supports.

0x0, ARM1136JF-S processors do not support this debug model.

[11:8]-

Indicates the type of embedded processor debug model that the processor supports.

0x0, ARM1136JF-S processors do not support this debug model.

[7:4]-

Indicates the type of Secure debug model that the processor supports.

0x0, ARM1136JF-S processors do not support a v6.1 Secure debug architecture model.

[3:0]-

Indicates the type of applications processor debug model that the processor supports.

0x2, ARM1136JF-S processors support the v6 debug model (CP 14-based).


Accessing the Debug Feature Register 0

Table 3.23 shows the results of attempted accesses to the Debug Feature Register 0 for each mode.

Table 3.23. Results of accesses to the Debug Feature Register 0
Privileged readPrivileged writeUser read or write
Data readUndefined Instruction exceptionUndefined Instruction exception

To access the Debug Feature Register 0 you read CP15 with:

  • Opcode_1 set to 0

  • CRn set to c0

  • CRm set to c1

  • Opcode_2 set to 2.

For example:

MRC p15, 0, <Rd>, c0, c1, 2               ; Read Debug Feature Register 0

c0, Auxiliary Feature Register 0

The purpose of the Auxiliary Feature Register 0 is to provide additional information about the features of the processor.

The Auxiliary Feature Register 0 is:

  • in CP15 c0

  • a 32-bit read-only register

  • accessible in privileged mode only

  • only available from the rev1 (r1p0) release of the ARM1136JF-S processor.

The contents of the Auxiliary Feature Register 0 are Implementation-defined. In the ARM1136JF-S processor, the Auxiliary Feature Register 0 reads as 0x00000000.

Accessing the Auxiliary Feature Register 0

Table 3.24 shows the results of attempted accesses to the Auxiliary Feature Register 0 for each mode.

Table 3.24. Results of accesses to the Auxiliary Feature Register 0
Privileged readPrivileged writeUser read or write
Data readUndefined Instruction exceptionUndefined Instruction exception

To access the Auxiliary Feature Register 0 you read CP15 with:

  • Opcode_1 set to 0

  • CRn set to c0

  • CRm set to c1

  • Opcode_2 set to 3.

For example:

MRC p15, 0, <Rd>, c0, c1, 3               ; Read Auxiliary Feature Register 0.

c0, Memory Model Feature Register 0

The purpose of the Memory Model Feature Register 0 is to provide information about the memory model, memory management, cache support, and TLB operations of the processor.

The Memory Model Feature Register 0 is:

  • in CP15 c0

  • a 32-bit read-only register

  • accessible in privileged mode only

  • only available from the rev1 (r1p0) release of the ARM1136JF-S processor.

Figure 3.17 shows the bit arrangement for Memory Model Feature Register 0.

Figure 3.17. Memory Model Feature Register 0 format

Figure 3.17. Memory Model Feature Register 0 format

Table 3.25 lists the bit functions of the Memory Model Feature Register 0.

Table 3.25. Memory Model Feature Register 0 bit functions
Bit rangeField nameFunction
[31:28]-

Reserved. RAZ.

[27:24]-

Indicates support for FCSE.

0x1, ARM1136JF-S processors support FCSE.

[23:20]-

Indicates support for the ARMv6 Auxiliary Control Register.

0x1, ARM1136JF-S processors support the Auxiliary Control Register.

[19:16]-

Indicates support for TCM and associated DMA.

0x3, ARM1136JF-S processors support ARMv6 TCM and DMA.

[15:12]-

Indicates support for cache coherency with DMA agent, shared memory.

0x0, ARM1136JF-S processors do not support this model.

[11:8]-

Indicates support for cache coherency support with CPU agent, shared memory.

0x0, ARM1136JF-S processors do not support this model.

[7:4]-

Indicates support for PMSA.

0x0, ARM1136JF-S processors do not support PMSA

[3:0]-

Indicates support for Virtual Memory System Architecture (VMSA).

0x3, ARM1136JF-S processors support:

  • VMSA v6 including cache and TLB type register

  • Extensions to ARMv6.


Accessing the Memory Model Feature Register 0

Table 3.26 shows the results of attempted accesses to the Memory Model Feature 0 register for each mode.

Table 3.26. Results of accesses to the Memory Model Feature Register 0
Privileged readPrivileged writeUser read or write
Data readUndefined Instruction exceptionUndefined Instruction exception

To access the Memory Model Feature Register 0 you read CP15 with:

  • Opcode_1 set to 0

  • CRn set to c0

  • CRm set to c1

  • Opcode_2 set to 4.

For example:

MRC p15, 0, <Rd>, c0, c1, 4           ; Read Memory Model Feature Register 0.

c0, Memory Model Feature Register 1

The purpose of the Memory Model Feature Register 1 is to provide information about the memory model, memory management, cache support, and TLB operations of the processor.

The Memory Model Feature Register 1 is:

  • in CP15 c0

  • a 32-bit read-only register

  • accessible in privileged mode only

  • only available from the rev1 (r1p0) release of the ARM1136JF-S processor.

Figure 3.18 shows the arrangement of bits in the register.

Figure 3.18. Memory Model Feature Register 1 format

Figure 3.18. Memory Model Feature Register 1 format

Table 3.27 lists the bit functions of the Memory Model Feature Register 1.

Table 3.27. Memory Model Feature Register 1 bit functions
Bit rangeField nameFunction
[31:28]-

Indicates support for branch target buffer.

0x1, ARM1136JF-S processors require flushing of branch target buffer on:

  • enabling or disabling the MMU

  • writing new data to instruction locations

  • writing new mappings to the page tables

  • any changes to the TTBR0, TTBR1, or TTBCR registers

  • any change of the FCSE ProcessID or ContextID.

[27:24]-

Indicates support for test and clean operations on data cache, Harvard or unified architecture.

0x0, no support in ARM1136JF-S processors.

[23:20]-

Indicates support for level one cache, all maintenance operations, unified architecture.

0x0, no support in ARM1136JF-S processors.

[19:16]-

Indicates support for level one cache, all maintenance operations, Harvard architecture.

0x3, ARM1136JF-S processors support:

  • invalidate instruction cache including branch target buffer

  • invalidate data cache

  • invalidate instruction and data cache including branch target buffer

  • clean data cache, recursive model using cache dirty status bit

  • clean and invalidate data cache, recursive model using cache dirty status bit.

[15:12]-

Indicates support for level one cache line maintenance operations by Set/Way, unified architecture.

0x0, no support in ARM1136JF-S processors.

[11:8]-

Indicates support for level one cache line maintenance operations by Set/Way, Harvard architecture.

0x3, ARM1136JF-S processors support:

  • clean data cache line by Set/Way

  • clean and invalidate data cache line by Set/Way

  • invalidate data cache line by Set/Way

  • invalidate instruction cache line by Set/Way.

[7:4]-

Indicates support for level one cache line maintenance operations by VA, unified architecture.

0x0, no support in ARM1136JF-S processors.

[3:0]-

Indicates support for level one cache line maintenance operations by VA, Harvard architecture.

0x2, ARM1136JF-S processors support:

  • clean data cache line by MVA

  • invalidate data cache line by MVA

  • invalidate instruction cache line by MVA

  • clean and invalidate data cache line by MVA

  • invalidation of branch target buffer by MVA.


Accessing the Memory Model Feature Register 1

Table 3.28 shows the results of attempted accesses to the Memory Model Feature Register 1 for each mode.

Table 3.28. Results of accesses to the Memory Model Feature Register 1
Privileged readPrivileged writeUser read or write
Data readUndefined Instruction exceptionUndefined Instruction exception

To access the Memory Model Feature Register 1 you read CP15 with:

  • Opcode_1 set to 0

  • CRn set to c0

  • CRm set to c1

  • Opcode_2 set to 5.

For example:

MRC p15, 0, <Rd>, c0, c1, 5           ; Read Memory Model Feature Register 1.

c0, Memory Model Feature Register 2

The purpose of the Memory Model Feature Register 2 is to provide information about the memory model, memory management, cache support, and TLB operations of the processor.

The Memory Model Feature Register 2 is:

  • in CP15 c0

  • a 32-bit read-only register

  • accessible in privileged mode only

  • only available from the rev1 (r1p0) release of the ARM1136JF-S processor.

Figure 3.19 shows the arrangement of bits in the register.

Figure 3.19. Memory Model Feature Register 2 format

Figure 3.19. Memory Model Feature Register 2 format

Table 3.29 lists the bit functions of the Memory Model Feature Register 2.

Table 3.29. Memory Model Feature Register 2 bit functions
Bit rangeField nameFunction
[31:28]-

Indicates support for a Hardware access flag.

0x0, Hardware access flag not supported by ARM1136JF-S processors.

[27:24]-

Indicates support for wait for interrupt stalling.

0x1, ARM1136JF-S processors support wait for interrupt.

[23:20]-

Indicates support for memory barrier operations.

0x2, ARM1136JF-S processors support:

  • data synchronization barrier (drain write buffer)

  • prefetch flush

  • data memory barrier.

[19:16]-

Indicates support for TLB maintenance operations, unified architecture.

0x2, ARM1136JF-S processors support:

  • invalidate all entries

  • invalidate TLB entry by MVA

  • invalidate TLB entries by ASID match.

[15:12]-

Indicates support for TLB maintenance operations, Harvard architecture.

0x2, ARM1136JF-S processors support:

  • invalidate instruction and data TLB, all entries

  • invalidate instruction TLB, all entries

  • invalidate data TLB, all entries

  • invalidate instruction TLB by MVA

  • invalidate data TLB by MVA

  • invalidate instruction and data TLB entries by ASID match

  • invalidate instruction TLB entries by ASID match

  • invalidate data TLB entries by ASID match.

[11:8]-

Indicates support for cache maintenance range operations, Harvard architecture.

0x1, ARM1136JF-S processors support:

  • invalidate data cache range by VA

  • invalidate instruction cache range by VA

  • clean data cache range by VA

  • clean and invalidate data cache range by VA.

[7:4]-

Indicates support for background prefetch cache range operations, Harvard architecture.

0x1, ARM1136JF-S processors support:

  • prefetch data cache range by VA

  • prefetch instruction cache range by VA.

[3:0]-

Indicates support for foreground prefetch cache range operations, Harvard architecture.

0x0, no support in ARM1136JF-S processors.


Accessing the Memory Model Feature Register 2

Table 3.30 shows the results of attempted accesses to the Memory Model Feature Register 2 for each mode.

Table 3.30. Results of accesses to the Memory Model Feature Register 2
Privileged readPrivileged writeUser read or write
Data readUndefined Instruction exceptionUndefined Instruction exception

To access the Memory Model Feature Register 2 you read CP15 with:

  • Opcode_1 set to 0

  • CRn set to c0

  • CRm set to c1

  • Opcode_2 set to 6.

For example:

MRC p15, 0, <Rd>, c0, c1, 6          ; Read Memory Model Feature Register 2.

c0, Memory Model Feature Register 3

The purpose of the Memory Model Feature Register 3 is to provide information about the memory model, memory management, cache support, and TLB operations of the processor.

The Memory Model Feature Register 3 is:

  • in CP15 c0

  • a 32-bit read-only register

  • accessible in privileged mode only

  • only available from the rev1 (r1p0) release of the ARM1136JF-S processor.

Figure 3.20 shows the arrangement of bits in the register.

Figure 3.20. Memory Model Feature Register 3 format

Figure 3.20. Memory Model Feature Register 3 format

Table 3.31 lists the bit functions of the Memory Model Feature Register 3.

Table 3.31. Memory Model Feature Register 3 bit functions
Bit rangeField nameFunction
[31:12]-

Reserved. RAZ.

[11:8}-

Indicates support for Branch Predictor maintenance, all architectures.

0x0, no support in ARM1136JF-S processors.

[7:4]-

Indicates support for hierarchical cache maintenance operations by MVA, all architectures.

0x0, no support in ARM1136JF-S processors.

[3:0]-

Indicates support for hierarchical cache maintenance operations by Set/Way, all architectures.

0x0, no support in ARM1136JF-S processors.


Accessing the Memory Model Feature Register 3

Table 3.32 shows the results of attempted accesses to the Memory Model Feature Register 3 for each mode.

Table 3.32. Results of accesses to the Memory Model Feature Register 3
Privileged readPrivileged writeUser read or write
Data readUndefined Instruction exceptionUndefined Instruction exception

To access the Memory Model Feature Register 3 you read CP15 with:

  • Opcode_1 set to 0

  • CRn set to c0

  • CRm set to c1

  • Opcode_2 set to 7.

For example:

MRC p15, 0, <Rd>, c0, c1, 7          ; Read Memory Model Feature Register 3.

c0, Instruction Set Attributes Register 0

The purpose of the Instruction Set Attributes Register 0 is to provide information about the instruction set that the processor supports beyond the basic set.

The Instruction Set Attributes Register 0 is:

  • in CP15 c0

  • a 32-bit read-only register

  • accessible in privileged mode only

  • only available from the rev1 (r1p0) release of the ARM1136JF-S processor.

Figure 3.21 shows the arrangement of bits in the register.

Figure 3.21. Instruction Set Attributes Register 0 format

Figure 3.21. Instruction Set Attributes Register
0 format

Table 3.33 lists the bit functions of the Instruction Set Attributes Register 0.

Table 3.33. Instruction Set Attributes Register 0 bit functions
Bit rangeField nameFunction
[31:28]-

Reserved. RAZ.

[27:24]Divide_instrs

Indicates support for divide instructions.

0x0, no support in ARM1136JF-S processors.

[23:20]Debug_instrs

Indicates support for debug instructions.

0x1, ARM1136JF-S processors support BKPT.

[19:16]Coproc_instrs

Indicates support for coprocessor instructions.

0x4, ARM1136JF-S processors support:

  • CDP, LDC, MCR, MRC, STC

  • CDP2, LDC2, MCR2, MRC2, STC2

  • MCRR, MRRC

  • MCRR2, MRRC2.

[15:12]CmpBranch_instrs

Indicates support for combined compare and branch instructions.

0x0, no support in ARM1136JF-S processors.

[11:8]Bitfield_instrs

Indicates support for bitfield instructions.

0x0, no support in ARM1136JF-S processors.

[7:4]BitCount_instrs

Indicates support for bit counting instructions.

0x1, ARM1136JF-S processors support CLZ.

[3:0]Atomic_instrs

Indicates support for atomic load and store instructions.

0x1, ARM1136JF-S processors support SWP and SWPB.


Accessing the Instruction Set Attributes Register 0

Table 3.34 shows the results of attempted accesses to the Instruction Set Attributes Register 0 for each mode.

Table 3.34. Results of accesses to the Instruction Set Attributes Register 0
Privileged readPrivileged writeUser read or write
Data readUndefined Instruction exceptionUndefined Instruction exception

To access the Instruction Set Attributes Register 0 you read CP15 with:

  • Opcode_1 set to 0

  • CRn set to c0

  • CRm set to c2

  • Opcode_2 set to 0.

For example:

MRC p15, 0, <Rd>, c0, c2, 0        ; Read Instruction Set Attributes Register 0

c0, Instruction Set Attributes Register 1

The purpose of the Instruction Set Attributes Register 1 is to provide information about the instruction set that the processor supports beyond the basic set.

The Instruction Set Attributes Register 1 is:

  • in CP15 c0

  • a 32-bit read-only register

  • accessible in privileged mode only

  • only available from the rev1 (r1p0) release of the ARM1136JF-S processor.

Figure 3.22 shows the arrangement of bits in the register.

Figure 3.22. Instruction Set Attributes Register 1 format

Figure 3.22. Instruction Set Attributes Register
1 format

Table 3.35 lists the bit functions of the Instruction Set Attributes Register 1.

Table 3.35. Instruction Set Attributes Register 1 bit functions
Bit rangeField nameFunction
[31:28]Jazelle_instrs

Indicates support for Jazelle instructions.

0x1, ARM1136JF-S processors support BXJ and J bit in PSRs.

[27:24]Interwork_instrs

Indicates support for interworking instructions.

0x2, ARM1136JF-S processors support:

  • BX, and T bit in PSRs

  • BLX, and PC loads have BX behavior.

[23:20]Imediate_instrs

Indicates support for immediate instructions.

0x0, no support in ARM1136JF-S processors.

[19:16]IfThen_instrs

Indicates support for If … Then instructions.

0x0, no support in ARM1136JF-S processors.

[15:12]Extend_instrs

Indicates support for sign or zero extend instructions.

0x2, ARM1136JF-S processors support:

  • SXTB, SXTB16, SXTH, UXTB, UXTB16, and UXTH

  • SXTAB, SXTAB16, SXTAH, UXTAB, UXTAB16, and UXTAH.

Shift operations on these instructions are also controlled by the WithShifts_instrs field, see c0, Instruction Set Attributes Register 4.

[11:8]Except2_instrs

Indicates support for exception 2 instructions.

0x1, ARM1136JF-S processors support SRS, RFE, and CPS.

[7:4]Except1_instrs

Indicates support for exception 1 instructions.

0x1, ARM1136JF-S processors support LDM(2), LDM(3) and STM(2).

[3:0]Endian_instrs

Indicates support for endianness control instructions.

0x1, ARM1136JF-S processors support SETEND and E bit in PSRs.


Accessing the Instruction Set Attributes Register 1

Table 3.36 shows the results of attempted accesses to the Instruction Set Attributes Register 1 for each mode.

Table 3.36. Results of accesses to the Instruction Set Attributes Register 1
Privileged readPrivileged writeUser read or write
Data readUndefined Instruction exceptionUndefined Instruction exception

To access the Instruction Set Attributes Register 1 you read CP15 with:

  • Opcode_1 set to 0

  • CRn set to c0

  • CRm set to c2

  • Opcode_2 set to 1.

For example:

MRC p15, 0, <Rd>, c0, c2, 1        ; Read Instruction Set Attributes Register 1

c0, Instruction Set Attributes Register 2

The purpose of the Instruction Set Attributes Register 2 is to provide information about the instruction set that the processor supports beyond the basic set.

The Instruction Set Attributes Register 2 is:

  • in CP15 c0

  • a 32-bit read-only register

  • accessible in privileged mode only

  • only available from the rev1 (r1p0) release of the ARM1136JF-S processor.

Figure 3.23 shows the arrangement of bits in the register.

Figure 3.23. Instruction Set Attributes Register 2 format

Figure 3.23. Instruction Set Attributes Register
2 format

Table 3.37 lists the bit functions of the Instruction Set Attributes Register 2.

Table 3.37. Instruction Set Attributes Register 2 bit functions
Bit rangeField nameFunction
[31:28]Reversal_instrs

Indicates support for reversal instructions.

0x1, ARM1136JF-S processors support REV, REV16, and REVSH.

[27:24]PSR_instrs

Indicates support for PSR instructions.

0x1, ARM1136JF-S processors support MRS and MRS exception return instructions for data-processing.

[23:20]MultU_instrs

Indicates support for advanced unsigned multiply instructions.

0x2, ARM1136JF-S processors support:

  • UMULL and UMLAL

  • UMAAL.

[19:16]MultS_instrs

Indicates support for advanced signed multiply instructions.

0x3, ARM1136JF-S processors support:

  • SMULL and SMLAL

  • SMLABB, SMLABT, SMLALBB, SMLALBT, SMLALTB, SMLALTT, SMLATB, SMLATT, SMLAWB, SMLAWT, SMULBB, SMULBT, SMULTB, SMULTT, SMULWB, SMULWT, and Q flag in PSRs

  • SMLAD, SMLADX, SMLALD, SMLALDX, SMLSD, SMLSDX, SMLSLD, SMLSLDX, SMMLA, SMMLAR, SMMLS, SMMLSR, SMMUL, SMMULR, SMUAD, SMUADX, SMUSD, and SMUSDX.

[15:12]Mult_instrs

Indicates support for multiply instructions.

0x1, ARM1136JF-S processors support MLA.

[11:8]MultiAccessInt_instrs

Indicates support for multi-access interruptible instructions.

0x1, ARM1136JF-S processors support restartable LDM and STM.

[7:4]MemHint_instrs

Indicates support for memory hint instructions.

0x1, ARM1136JF-S processors support PLD.

[3:0]LoadStore_instrs

Indicates support for load and store instructions.

0x1, ARM1136JF-S processors support LDRD and STRD.


Accessing the Instruction Set Attributes Register 2

Table 3.38 shows the results of attempted accesses to the Instruction Set Attributes Register 2 for each mode.

Table 3.38. Results of accesses to the Instruction Set Attributes Register 2
Privileged readPrivileged writeUser read or write
Data readUndefined Instruction exceptionUndefined Instruction exception

To access the Instruction Set Attributes Register 2 you read CP15 with:

  • Opcode_1 set to 0

  • CRn set to c0

  • CRm set to c2

  • Opcode_2 set to 2.

For example:

MRC p15, 0, <Rd>, c0, c2, 2        ; Read Instruction Set Attributes Register 2

c0, Instruction Set Attributes Register 3

The purpose of the Instruction Set Attributes Register 3 is to provide information about the instruction set that the processor supports beyond the basic set.

The Instruction Set Attributes Register 3 is:

  • in CP15 c0

  • a 32-bit read-only register

  • accessible in privileged mode only

  • only available from the rev1 (r1p0) release of the ARM1136JF-S processor.

Figure 3.24 shows the arrangement of bits in the register.

Figure 3.24. Instruction Set Attributes Register 3 format

Figure 3.24. Instruction Set Attributes Register
3 format

Table 3.39 lists the bit functions of the Instruction Set Attributes Register 3.

Table 3.39. Instruction Set Attributes Register 3 bit functions
Bit rangeField nameFunction
[31:28]T2ExeEnvExtn_instrs

Indicates support for Thumb-2 execution environment extensions.

0x0, no support in ARM1136JF-S processors.

[27:24]TrueNOP_instrs

Indicates support for true NOP instructions.

0x1, ARM1136JF-S processors support true NOP (NOP32) and the capability for additional NOP compatible hints. ARM1136JF-S processors do not support NOP16.

[23:20]ThumbCopy_instrs

Indicates support for Thumb copy instructions.

0x1, ARM1136JF-S processors support Thumb MOV(3) low register ⇒ low register, and the CPY alias for Thumb MOV(3).

[19:16]TabBranch_instrs

Indicates support for table branch instructions.

0x0, no support in ARM1136JF-S processors.

[15:12]SynchPrim_instrs

Indicates support for synchronization primitive instructions.

0x2, ARM1136JF-S processors support:

  • LDREX and STREX

  • LDREXB, LDREXH, LDREXD, STREXB, STREXH, STREXD, and CLREX.

[11:8]SWI_instrs

Indicates support for SWI instructions.

0x1, ARM1136JF-S processors support SWI.

[7:4]SIMD_instrs

Indicates support for Single Instruction Multiple Data (SIMD) instructions.

0x3, ARM1136JF-S processors support:

PKHBT, PKHTB, QADD16, QADD8, QADDSUBX, QSUB16, QSUB8, QSUBADDX, SADD16, SADD8, SADDSUBX, SEL, SHADD16, SHADD8, SHADDSUBX, SHSUB16, SHSUB8, SHSUBADDX, SSAT, SSAT16, SSUB16, SSUB8, SSUBADDX, SXTAB16, SXTB16, UADD16, UADD8, UADDSUBX, UHADD16, UHADD8, UHADDSUBX, UHSUB16, UHSUB8, UHSUBADDX, UQADD16, UQADD8, UQADDSUBX, UQSUB16, UQSUB8, UQSUBADDX, USAD8, USADA8, USAT, USAT16, USUB16, USUB8, USUBADDX, UXTAB16, UXTB16, and the GE[3:0] bits in the PSRs.

[3:0]Saturate_instrs

Indicates support for saturate instructions.

0x1, ARM1136JF-S processors support QADD, QDADD, QDSUB, QSUB and Q flag in PSRs.


Accessing the Instruction Set Attributes Register 3

Table 3.40 shows the results of attempted accesses to the Instruction Set Attributes Register 3 for each mode.

Table 3.40. Results of accesses to the Instruction Set Attributes Register 3
Privileged readPrivileged writeUser read or write
Data readUndefined Instruction exceptionUndefined Instruction exception

To access the Instruction Set Attributes Register 3 you read CP15 with:

  • Opcode_1 set to 0

  • CRn set to c0

  • CRm set to c2

  • Opcode_2 set to 3.

For example:

MRC p15, 0, <Rd>, c0, c2, 3        ; Read Instruction Set Attributes Register 3

c0, Instruction Set Attributes Register 4

The purpose of the Instruction Set Attributes Register 4 is to provide information about the instruction set that the processor supports beyond the basic set.

The Instruction Set Attributes Register 4 is:

  • in CP15 c0

  • a 32-bit read-only register

  • accessible in privileged mode only

  • only available from the rev1 (r1p0) release of the ARM1136JF-S processor.

Figure 3.25 shows the arrangement of bits in the register.

Figure 3.25. Instruction Set Attributes Register 4 format

Figure 3.25. Instruction Set Attributes Register
4 format

Table 3.41 lists the bit functions of the Instruction Set Attributes Register 4.

Table 3.41. Instruction Set Attributes Register 4 bit functions
Bit rangeField nameFunction
[31:28]-

Reserved. RAZ.

[27:24]-

Reserved. RAZ.

[23:20]Syncprim_instrs_frac

Indicates fractional support for synchronization primitive instructions.

0x0, ARM1136JF-S processors do not have fractional support.

The SynchPrim_instrs field indicates the support for synchronization primitive instructions, see c0, Instruction Set Attributes Register 3.

[19:16]Barrier_instrs

Indicates support for barrier instructions.

0x0, ARM1136JF-S processors use CP15 operations for all barrier instructions.

[15:12]SMI_instrs

Indicates support for SMI instructions.

0x0, ARM1136JF-S processors do not support SMI.

[11:8]Writeback_instrs

Indicates support for writeback instructions.

0x1, ARM1136JF-S processors support all defined writeback addressing modes.

[7:4]WithShifts_instrs

Indicates support for with shift instructions.

0x4, ARM1136JF-S processors support:

  • shifts of loads and stores over the range LSL 0-3

  • constant shift options

  • register controlled shift options.

[3:0]Unpriv_instrs

Indicates support for Unprivileged instructions.

0x1, ARM1136JF-S processors support LDRBT, LDRT, STRBT, and STRT.


Accessing the Instruction Set Attributes Register 4

Table 3.42 shows the results of attempted accesses to the Instruction Set Attributes Register 4 for each mode.

Table 3.42. Results of accesses to the Instruction Set Attributes Register 4
Privileged readPrivileged writeUser read or write
Data readUndefined Instruction exceptionUndefined Instruction exception

To access the Instruction Set Attributes Register 4 you read CP15 with:

  • Opcode_1 set to 0

  • CRn set to c0

  • CRm set to c2

  • Opcode_2 set to 4.

For example:

MRC p15, 0, <Rd>, c0, c2, 4        ; Read Instruction Set Attributes Register 4

c0, Instruction Set Attributes Register 5

The purpose of the Instruction Set Attributes Register 5 is to provide additional information about the properties of the processor.

The Instruction Set Attributes Register 5 is:

  • in CP15 c0

  • a 32-bit read-only register

  • accessible in privileged mode only

  • only available from the rev1 (r1p0) release of the ARM1136JF-S processor.

In the ARM1136JF-S processor, Instruction Set Attributes Register 5 reads as 0x00000000.

Accessing the Instruction Set Attributes Register 5

Table 3.43 shows the results of attempted accesses to the Instruction Set Attributes Register 5 for each mode.

Table 3.43. Results of accesses to the Instruction Set Attributes Register 5
Privileged readPrivileged writeUser read or write
Data readUndefined Instruction exceptionUndefined Instruction exception

To access the Instruction Set Attributes Register 5 you read CP15 with:

  • Opcode_1 set to 0

  • CRn set to c0

  • CRm set toc2

  • Opcode_2 set to 5.

For example:

MRC p15, 0, <Rd>, c0, c2, 5        ; Read Instruction Set Attribute Register 5.