The purpose of the Main ID Register is to return the device ID code that contains information about the processor.
The Main ID Register is:
in CP15 c0
a 32 bit read-only register
accessible in privileged mode only.
Before the r1p0 release, this register was called the ID Code Register.
Figure 3.9 shows the arrangement of bits in the register.
The contents of the Main ID Register depend on the specific implementation. Table 3.4 lists the bit functions of the Main ID Register.
|Bit range||Field name|
|Indicates the implementer, ARM Limited.|
|[23:20]||Variant number||The major revision number n of the rnpn revision status, see Product revision status.|
Primary part number
Part number for ARM1136JF-S and ARM1136J-S
|The minor revision number n of the rnpn revision status, see Product revision status.|
given is for the rev1 (r1pn) releases of the ARM1136JF-S processor.
For rev0 (r0pn) releases, the Variant number is
[b] For example, for the r1p5 release of the ARM1136 processors, this value is 0x5.
If the processor encounters an Opcode_2 value corresponding to an unimplemented or reserved ID register with CRm = c0 and Opcode_1 = 0, the system control coprocessor returns the value of the Main ID Register.
Table 3.5 shows the results of attempted accesses to the Main ID Register for each mode.
|Privileged read||Privileged write||User read or write|
|Data read||Undefined Instruction exception||Undefined Instruction exception|
To access the Main ID Register you read CP15 with:
Opcode_1 set to 0
CRn set to c0
CRm set to c0
Opcode_2 set to 0.
MRC p15,0,<Rd>,c0,c0,0 ; Read Main ID Register
For more information about the processor features, see c0, Core feature ID registers.