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3.3.3. c0, TCM Status Register

The purpose of the TCM Status Register is to inform the system about the number of Instruction and Data TCMs available in the processor.

Note

The ARM1136JF-S processor implements only one Instruction TCM and one Data TCM.

The TCM Status Register is:

  • in CP15 c0

  • a 32-bit read-only register

  • accessible in privileged mode only.

Figure 3.12 shows the arrangement of bits in the register.

Figure 3.12. TCM Status Register format

Figure 3.12. TCM Status Register format

Table 3.14 lists the bit functions of the TCM Status Register.

Table 3.14. TCM Status Register field descriptions
BitsField nameDescription
[31:29]-Always 0.
[28:19]- SBZ/UNP.
[18:16]DTCM

Specifies the number of Data TCMs implemented.

For ARM1136JF-S processors this value is 1.

[15:3]-SBZ/UNP.
[11:0]ITCM

Specifies the number of Instruction TCMs implemented.

For ARM1136JF-S processors this value is 1.


Accessing the TCM Status Register

Table 3.15 shows the results of attempted accesses to the TCM Status Register for each mode.

Table 3.15. Results of accesses to the TCM Status Register
Privileged readPrivileged writeUser read or write
Data readUndefined Instruction exceptionUndefined Instruction exception

To access the TCM Status Register you read CP15 c0 with:

  • Opcode_1 set to 0

  • CRn set to c0

  • CRm set to c0

  • Opcode_2 set to 2.

For example:

MRC p15,0,<Rd>,c0,c0,2                 ; returns TCM status register