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3.3.8. c1, Coprocessor Access Control Register

The purpose of the Coprocessor Access Control Register is to set access rights for all coprocessors other than CP14 and CP15. This register also provides a means for software to test if any particular coprocessor, CP0-CP13, exists in the system.

This register has no effect on access to CP14, the debug control coprocessor, or CP15, the system control coprocessor.

The Coprocessor Access Control Register is:

  • in CP15 c1

  • a 32-bit read/write register

  • accessible in privileged mode only.

Figure 3.28 shows the arrangement of bits in the register.

Figure 3.28. Coprocessor Access Control Register format

Figure 3.28. Coprocessor Access Control Register

Table 3.49 lists the bit functions of the Coprocessor Access Control Register.

Table 3.49. Coprocessor Access Control Register field descriptions
Bit rangeField nameFunction

Reserved. This field is UNP/RAZ when read. Write as the existing value.


Defines access permissions coprocessor <n>[b]. See Table 3.50 for the permitted values for this field.

If a coprocessor does not exist, any write to the corresponding cp field is ignored.

On reset, each of these fields is set to 0b00, Access denied.

[a] There are 14 two-bit cp fields. See Figure 3.28 for the bit range for each field.

[b] n is the coprocessor number, between 0 and 13.

Table 3.50 shows the possible bit-pair access rights encodings for each coprocessor connected to the ARM1136JF-S processor.

Table 3.50. Coprocessor access rights encodings

Access denied.

Attempts to access the corresponding coprocessor generate an Undefined Instruction exception.

b01Privileged mode (Supervisor) access only.
b11Full access.

Accessing the Coprocessor Access Control Register

Table 3.51 shows the results of attempted accesses to the Coprocessor Access Control Register for each mode.

Table 3.51. Results of accesses to the Coprocessor Access Control Register
Privileged readPrivileged writeUser read or write
Data readData writeUndefined Instruction exception

To access the Coprocessor Access Control Register you read or write CP15 with:

  • Opcode_1 set to 0

  • CRn set to c1

  • CRm set to c0

  • Opcode_2 set to 2.

For example:

MRC p15, 0, <Rd>, c1, c0, 2       ; Read Coprocessor Access Control Register
MCR p15, 0, <Rd>, c1, c0, 2      ; Write Coprocessor Access Control Register

You must execute an Instruction Memory Barrier (IMB) sequence immediately after updating the Coprocessor Access Control Register, see Instruction Memory Barrier (IMB) instruction. When you update the Coprocessor Access Control Register you must not attempt to execute any instructions that are affected by the change of access rights until you have executed the IMB sequence.


ARM recommends that you access this register using a read-modify-write sequence.

You can use the Coprocessor Access Control Register to find whether a particular coprocessor exists in the system by:

  • Writing a permitted value other than 0b00 to the access permissions field of the coprocessor you are interested in.

  • Read back the Coprocessor Access Control Register. If the coprocessor does not exist in the system field then its access rights remain set to 0b00.

After a system reset, all coprocessor access rights are set to 0b00, access denied.