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3.3.33. c11, DMA Channel Status Registers

Each implemented DMA channel has its own DMA Channel Status Register. The purpose of each DMA Channel Status Register is to define the status of the most recently started DMA operation on that channel.

The DMA Channel Status Registers are:

  • in CP15 c11

  • one 32-bit read-only register for each DMA channel

  • accessible in user and privileged modes

    • a DMA Channel Status Register is only accessible in User mode if the U bit of the currently selected DMA channel is set to 1 in the DMA User Accessibility Register, see c11, DMA User Accessibility Register for details.

Figure 3.55 shows the arrangement of bits in the registers.

Figure 3.55. DMA Channel Status Register format

Figure 3.55. DMA Channel Status Register format

Table 3.122 shows the bit functions of the DMA Channel Status Registers.

Table 3.122. DMA Channel Status Register bit functions
Bit rangeField nameFunction
[31:13]-

UNP/SBZ.

[12]BP

Indicates whether the DMA parameters are acceptable, or are conditioned inappropriately:

0 = DMA parameters are acceptable. This is the reset value

1 = DMA parameters are conditioned inappropriately.

The external start and end addresses, and the Stride must all be multiples of the transaction size. If this is not the case, the BP bit is set to 1, and the DMA channel does not start.

[11:7]ES

External address error Status. Indicates the status of the External Address Error:

b00000 = No error. This is the reset value.

b00xxx = No error.

b01001 = Unshared data error.

b10011 = Access Flag fault, section.

b10110 = Access Flag fault, page.

b11010 = External Abort (can be imprecise).

b11100 = External Abort on translation of first-level page table.

b11110 = External Abort on translation of second-level page table.

b10101 = Translation fault, section.

b10111 = Translation fault, page.

b11001 = Domain fault, section.

b11011 = Domain fault, page.

b11101 = Permission fault, section.

b11111 = Permission fault, page.

All other encodings are Reserved.

[6:2]IS

Internal address error Status. Indicates the status of the Internal Address Error:

b01000 = TCM out of range

b10011 = Access Flag fault, section

b10110 = Access Flag fault, page

b11100 = External Abort on translation of first-level page table

b11110 = External Abort on translation of second-level page table

b10101 = Translation fault, section

b10111 = Translation fault, page

b11001 = Domain fault, section

b11011 = Domain fault, page

b11101 = Permission fault, section

b11111 = Permission fault, page.

All other encodings are Reserved.

[1:0]Status

Indicates the status of the DMA channel:

b00 = Idle. This is the reset value.

b01 = Queued.

b10 = Running.

b11 = Complete or Error.


Accessing the DMA Channel Status Registers

The value held in the DMA Channel Number Register determines whether the channel 0 or the channel 1 DMA Channel Status Register will be accessed. See c11, DMA Channel Number Register for details.

Table 3.115 shows the results of attempted accesses to a DMA Internal End Address Register for each mode.

Table 3.123. Results of accesses to a DMA Channel Status Register
U bit[a]Privileged readPrivileged writeUser readUser write
0Data readUndefined Instruction exceptionUndefined Instruction exceptionUndefined Instruction exception
1Data readUndefined Instruction exceptionData readUndefined Instruction exception

[a] In the DMA User Accessibility Register. See c11, DMA User Accessibility Register for details. The values given are for the U bit of the currently selected DMA channel, see c11, DMA Channel Number Register for more information.


To access a DMA Channel Status Register you:

  • Write to the DMA Channel Number Register to select the DMA channel you want to access, see c11, DMA Channel Number Register.

  • Read CP15 with:

    • Opcode_1 set to 0

    • CRn set to c11

    • CRm set to c8

    • Opcode_2 set to 0.

    For example:

    MRC p15, 0, <Rd>, c11, c8, 0            ; Read DMA Channel Status Register
    

Using the DMA Channel Status Registers

In the event of an error, the appropriate Start Address Register contains the address that faulted, unless the error is an external error that is set to b11010 by bits[11:7].

A channel with the state of Queued changes to Running automatically if the other channel (if implemented) changes to Idle, or Complete or Error, with no error.

When a channel has completed all of the transfers of the DMA, so that all changes to memory locations caused by those transfers are visible to other observers, its status is changed from Running to Complete or Error. This change does not happen before the external accesses from the transfer have completed.

If the processor attempts to access memory locations that are not marked as shared, then the ES bits signal an Unshared error for either:

  • a DMA transfer in User mode

  • a DMA transfer that has the UM bit set in the DMA Control Register.

A DMA transfer where the external address is within the range of the TCM also results in an Unshared data error.