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3.3.34. c11, DMA Context ID Registers

Each implemented DMA channel has its own DMA Context ID Register. The purpose of each DMA Context ID Register is to contain the processor 32-bit Context ID of the process that is using that channel.

The DMA Context ID Registers are:

  • in CP15 c11

  • a 32-bit read/write register for each DMA channel

  • accessible in privileged mode only.

Figure 3.56 shows the arrangement of bits in the register.

Figure 3.56. DMA Context ID Register format

Figure 3.56. DMA Context ID Register format

Table 3.124 shows the bit functions of the DMA Context ID Registers.

Table 3.124. DMA Context ID Register bit functions
Bit rangeField nameFunction

Extends the ASID to form the process ID and identify the current process.

Holds the process ID value.


Holds the ASID of the current process and identifies the current ASID.

Accessing the DMA Context ID Registers

Table 3.125 shows the results of attempted accesses to a DMA Context ID Register for each mode.

Table 3.125. Results of accesses to the DMA Context ID Register
Privileged readPrivileged writeUser read or write
Data readData writeUndefined Instruction exception

To access a DMA Context ID Register you:

  • Write to the DMA Channel Number Register to select the DMA channel you want to access, see c11, DMA Channel Number Register.

  • Read or write CP15 with:

    • Opcode_1 set to 0

    • CRn set to c11

    • CRm set to c15

    • Opcode_2 set to 0.

    For example:

    MRC p15, 0, <Rd>, c11, c15, 0            ; Read DMA Context ID Register
    MCR p15, 0, <Rd>, c11, c15, 0            ; Write DMA Context ID Register

Using the DMA Context ID Registers

The DMA Context ID Register must be written with the processor Context ID of the process using the channel as part of the initialization of that channel. Where the channel is designated as a User-accessible channel, the Context ID must be written by the privileged process that initializes the channel for User use at the same time that the U bit for the channel is written to.

The bottom eight bits of the Context ID register are used in the address translation from virtual to physical addresses to enable different Virtual Address maps to co-exist. Attempting to write this register while the DMA channel is Running or Queued has no effect.

The bottom eight bits of the Context ID register are accessible to the AHB memory on DMAASID[7:0].

This register can only be read by a privileged process. This provides anonymity of the DMA channel usage from User processes. It can only be written by a privileged process for security reasons. On a context switch, where the state of the DMA is being stacked and restored, you must include this register in the saved state.