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3.3.29. c11, DMA Control Registers

Each implemented DMA channel has its own DMA Control Register. The purpose of each DMA Control Register is to control the operation of that DMA channel.

The DMA Control Registers are:

  • in CP15 c11

  • one 32-bit read/write register for each DMA channel

  • accessible in user and privileged modes

    • a DMA Control Register is only accessible in User mode if the U bit of the currently selected DMA channel is set to 1 in the DMA User Accessibility Register, see c11, DMA User Accessibility Register for details.

Figure 3.9 shows the arrangement of bits in the registers.

Figure 3.54. DMA Control Register format

Figure 3.54. DMA Control Register format

Table 3.117 shows the bit functions of the DMA Control Registers.

Table 3.117. DMA Control Register bit functions
Bit rangeField nameFunction
[31]TR

TaRget. Indicates target TCM:

0 = Data TCM. This is the reset value

1 = Instruction TCM.

[30]DT

Direction of Transfer:

0 = Transfer from level two memory to the TCM. This is the reset value

1 = Transfer from the TCM to the level two memory.

[29]IC

Interrupt on Completion. Indicates whether the DMA channel must assert an interrupt on completion of the DMA transfer, or if the DMA is stopped by a Stop command, see c11, DMA Enable Registers.

The interrupt is deasserted, from this source, if the processor performs a Clear operation on the channel that caused the interrupt. For more details see c11, DMA Enable Registers.

The U bit[a] has no effect on whether an interrupt is generated on completion.

0 = No Interrupt on Completion, reset value.

1 = Interrupt on Completion.

[28]IE

Interrupt on Error. Indicates that the DMA channel must assert an interrupt on an error.

The interrupt is deasserted (from this source) when the channel is set to Idle with a Clear operation, see c11, DMA Enable Registers.

0 = No Interrupt on Error, if the U bit is 0, reset value.

1 = Interrupt on Error, regardless of the U bit[a]. All DMA transactions on channels that have the U bit set to 1 Interrupt on Error regardless of the value written to this bit.

[27]FT

Full Transfer. Indicates that the DMA transfers all words of data as part of the DMA that is transferring data from the TCM to the external memory:

0 = Transfer at least those locations in the address range of the DMA in the TCM that have been changed by a store operation since the location was written to or read from by an earlier DMA

1 = Transfer all locations in the address range of the DMA, regardless of whether or not the locations have been changed by a store.

[26]UM

User Mode. Indicates whether the permission checks are based on the DMA being in User mode or in a privileged mode.

The UM bit is provided so that a privileged mode process can emulate User mode accesses. For a User mode process the processor ignores the setting of the UM bit and behaves as if it is set to 1.

0 = Transfer is a privileged transfer, reset value.

1 = Transfer is a User mode transfer.

If the U bit for a channel is set to 1 in the DMA User Accessibility Register, the processor ignores the UM bit value, and the channel behaves as if UM is set to 1. See c11, DMA User Accessibility Register for more information.

[25:20]-

UNP/SBZ.

[19:8]ST

STride (in bytes). Indicates the increment on the external address between each consecutive access of the DMA. A Stride of zero, reset value, indicates that the external address is not to be incremented. This is designed to facilitate the accessing of volatile locations such as a FIFO.

The Stride is interpreted as a positive number (or zero), and he STride value is in bytes.

The internal address increment is not affected by the Stride, but is fixed at the transaction size.

The value of the Stride must be aligned to the Transaction Size, otherwise this results in a bad parameter error, see c11, DMA Channel Status Registers.

[7:2]-

UNP/SBZ.

[1:0]TS

Transaction Size. Indicates the size of the transactions that the DMA channel performs. This is particularly important for Device or Strongly Ordered memory locations because it ensures that accesses to such memory occur at their programmed size.

b00 = Byte. This is the reset value.

b01 = Halfword.

b10 = Word.

b11 = Doubleword, 8 bytes.


Note

Setting the FT bit to 0 causes the DMA to look for dirty information, at a granularity of four words, for the data TCM. That is, if any word/byte within a four-word range (aligned to a four-word boundary) has been written to, then these four words are written back. The FT bit has no effect for transfers from the Instruction TCM.

Accessing the DMA Control Registers

The value held in the DMA Channel Number Register determines whether the channel 0 or the channel 1 DMA Control Register will be accessed. See c11, DMA Channel Number Register for details.

Table 3.115 shows the results of attempted accesses to the DMA Control Registers for each mode.

Table 3.118. Results of accesses to the DMA Control Registers
U bit[a]Privileged readPrivileged writeUser readUser write
0Data readData writeUndefined Instruction exceptionUndefined Instruction exception
1Data readData writeData readData write

[a] In the DMA User Accessibility Register. See c11, DMA User Accessibility Register for details. The values given are for the U bit of the currently selected DMA channel, see c11, DMA Channel Number Register for more information.


To access a DMA Control Register you:

  • Write to the DMA Channel Number Register to select the DMA channel you want to access, see c11, DMA Channel Number Register.

  • Write CP15 with:

    • Opcode_1 set to 0

    • CRn set to c11

    • CRm set to c4

    • Opcode_2 set to 0.

    For example:

    MRC p15, 0, <Rd>, c11, c4, 0            ; Read DMA Control Register
    
    MCR p15, 0, <Rd>, c11, c4, 0            ; Write DMA Control Register
    

While the currently selected channel has the status of Running or Queued, any attempt to write to the DMA Control Register results in architecturally Unpredictable behavior. For ARM1136JF-S processors writes to the DMA Control Register have no effect when the DMA channel is running or queued.