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3.3.28. c11, DMA Enable Registers

The purpose of the DMA Enable Registers is to start, stop or clear DMA transfers for each channel implemented.

The DMA enable registers are:

  • in CP15 c11

  • three 32-bit write only registers for each DMA channel. For each channel, the three registers provide the following three commands:

    • Stop (Opcode_2 = 0)

    • Start (Opcode_2 = 1)

    • Clear (Opcode_2 = 2)

  • accessible in User and privileged modes

    • the registers are only accessible in User mode if the U bit of the currently selected DMA channel is set to 1 in the DMA User Accessibility Register, see c11, DMA User Accessibility Register for details.

The commands provided by these registers are:

Stop

The DMA channel ceases to do memory accesses as soon as possible after the level one DMA issues the Stop instruction. This acceleration approach cannot be used for DMA transactions to or from memory regions marked as Device. The DMA can issue a Stop command when the channel status is Running.

The DMA channel can take several cycles to stop after the DMA issues a Stop instruction. The channel status remains at Running until the DMA channel stops. The channel status is set to Complete or Error at the point when all outstanding memory accesses complete. When the channel stops, the Start Address Registers contain the addresses the DMA requires to restart the operation.

If the Stop command occurs when the channel status is Queued, the channel status changes to Idle. The Stop command has no effect if the channel status is not Running or Queued.

c11, DMA Channel Status Registers describes the DMA channel status.

Start

The Start command causes the channel to start DMA transfers. If the other DMA channel is not in operation the channel status is set to Running on the execution of a Start command. If the other DMA channel is in operation the channel status is set to Queued.

A channel is in operation if any of the following apply:

  • its channel status is Queued

  • its channel status is Running

  • its channel status is Complete or Error, with either the Internal or External Address Error Status indicating an Error.

c11, DMA Channel Status Registers describes DMA channel status.

Clear

The Clear command causes the channel status to change from Complete or Error to Idle. It also clears:

  • all the Error bits for that DMA channel

  • the interrupt that is set by the DMA channel as a result of an error or completion, see c11, DMA Control Registers for more details.

The Clear command does not change the contents of the Internal and External Start Address Registers. A Clear command has no effect when the channel status is Running or Queued.

Accessing the DMA Enable Registers

The value held in the DMA Channel Number Register determines whether the channel 0 or the channel 1 DMA Enable Registers will be accessed. See c11, DMA Channel Number Register for details.

Table 3.115 shows the results of attempted accesses to the DMA Enable Registers for each mode.

Table 3.115. Results of accesses to the DMA Enable Registers
U bit[a]Privileged readPrivileged writeUser readUser write
0Undefined Instruction exceptionData writeUndefined Instruction exceptionUndefined Instruction exception
1Undefined Instruction exceptionData writeUndefined Instruction exceptionData write

[a] In the DMA User Accessibility Register. See c11, DMA User Accessibility Register for details. The values given are for the U bit of the currently selected DMA channel, see c11, DMA Channel Number Register for more information.


To access the DMA Enable Registers you:

  • Write to the DMA Channel Number Register to select the DMA channel you want to access, see c11, DMA Channel Number Register.

  • Write CP15 with:

    • Opcode_1 set to 0

    • CRn set to c11

    • CRm set to c3

    • Opcode_2 set to select the register for the required operation, see Table 3.116.

    For example:

    MCR p15, 0, <Rd>, c11, c3, 0            ; Stop DMA Enable Register
    
    MCR p15, 0, <Rd>, c11, c3, 1            ; Start DMA Enable Register
    
    MCR p15, 0, <Rd>, c11, c3, 2            ; Clear DMA Enable Register
    

Table 3.116 shows the Opcode_2 values used to select the appropriate DMA Enable Register for the required operation.

Table 3.116. DMA Enable Register selection
Opcode_2Operation
0Stop
1Start
2Clear
3-7Reserved

Debug implications for the DMA

The level one DMA behaves as a separate engine from the processor core, and when started works autonomously. As a result, if the level one DMA has channels with the status of Running or Queued, then these channels continue to run, or start running, even if the processor is stopped by debug mechanisms. This results in the contents of the TCM changing while the processor is stopped in debug. The DMA channels must be stopped by a Stop operation to avoid this situation.