Each implemented DMA channel has its own DMA Internal End Address Register. The purpose of each DMA Internal End Address Register is to define the final internal address for that channel. This is, the end address of the data transfer.
The DMA Internal End Address Registers are:
in CP15 c11
one 32-bit read/write register for each DMA channel
accessible in user and privileged modes
a DMA Internal End Address Register is only accessible in User mode if the U bit of the currently selected DMA channel is set to 1 in the DMA User Accessibility Register, see c11, DMA User Accessibility Register for details.
The DMA Internal End Address Register bits [31:0] contain the Internal End VA.
The value held in the DMA Channel Number Register determines whether the channel 0 or the channel 1 DMA Internal End Address Register will be accessed. See c11, DMA Channel Number Register for details.
Table 3.115 shows the results of attempted accesses to a DMA Internal End Address Register for each mode.
|U bit[a]||Privileged read||Privileged write||User read||User write|
|0||Data read||Data write||Undefined Instruction exception||Undefined Instruction exception|
|1||Data read||Data write||Data read||Data write|
To access a DMA Internal End Address Register you:
Write to the DMA Channel Number Register to select the DMA channel you want to access, see c11, DMA Channel Number Register.
Write CP15 with:
Opcode_1 set to 0
CRn set to c11
CRm set to c7
Opcode_2 set to 0.
MRC p15, 0, <Rd>, c11, c7, 0 ; Read DMA Internal End Address Register
MCR p15, 0, <Rd>, c11, c7, 0 ; Write DMA Internal End Address Register
This register defines the Internal End Address. The Internal End Address is the final internal address, modulo the transaction size, that the DMA is to access plus the transaction size. Therefore the Internal End Address is the first (incremented) address that the DMA does not access.
If the Internal End Address is the same of the Internal Start Address, the DMA transfer completes immediately without performing transactions.
When the transaction associated with the final internal address has completed, the whole DMA transfer is complete.
The Internal End Address is a VA. Page tables describe the physical mapping of the VA when the channel starts. The memory attributes for that VA are used in the transfer, so memory permission faults might be generated. The Internal End Address must lie within a TCM, otherwise an error is reported in the DMA Channel Status Register. The marking of memory locations in the TCM as being Device results in Unpredictable effects.
The Internal End Address must be aligned to the transaction size set in the DMA Control Register or the effects are Unpredictable.
Attempting to write to this register while the DMA channel is Running or Queued has no effect. That is, the operation fails without issuing an error.