CP15 register c11 accesses the DMA registers. The value of the CRm field determines which register is accessed. Table 3.107 shows the values of CRm that are used to access the available DMA registers.
|DMA Identification and Status Registers||c0||Present, Queued, Running, or Interrupting||Privileged only, Read-only||-||c11, DMA Identification and Status Registers|
|DMA User Accessibility Register||c1||0||Privileged only, Read/write||-||c11, DMA User Accessibility Register|
|DMA Channel Number Register||c2||0||Read/write||-||c11, DMA Channel Number Register|
|DMA Enable Register||c3||Stop, Start, or Clear||Write-only||One register per channel||c11, DMA Enable Registers|
|DMA Control Register||c4||0||Read/write||One register per channel||c11, DMA Control Registers|
|DMA Internal Start Address Register||c5||0||Read/write||One register per channel||c11, DMA Internal Start Address Registers|
|DMA External Start Address Register||c6||0||Read/write||One register per channel||c11, DMA External Start Address Registers|
|DMA Internal End Address Register||c7||0||Read/write||One register per channel||c11, DMA Internal End Address Registers|
|DMA Channel Status Register||c8||0||Read-only||One register per channel||c11, DMA Channel Status Registers|
|DMA Context ID Register||c15||0||Privileged only, Read/write||One register per channel||c11, DMA Context ID Registers|
The Enable, Control, Internal Start Address, External Start Address, Internal End Address, Channel Status, and Context ID registers are multiple registers, with one register of each for each channel that is implemented. The register accessed is determined by the DMA Channel Number Register, as described in c11, DMA Channel Number Register.
As shown in Table 3.107, most CP15 c11 operations can be executed by code while in User mode. The detailed register descriptions which follow include the results of attempted accesses for each mode.
Attempting to execute a privileged operation in User mode using CP15 c11 results in the Undefined Instruction trap being taken.