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3.3.35. c13, FCSE PID Register

The Context ID Register replaces the FCSE PID register, and use of the FCSE PID Register is deprecated. For more information see c13, Context ID Register.

The FCSE PID Register is:

  • in CP15 c13

  • a 32-bit read/write register

  • accessible in privileged mode only.

Figure 3.57 shows the arrangement of bits in the register.

Figure 3.57. FCSE PID Register format

Figure 3.57. FCSE PID Register format

Table 3.126 shows the bit functions of the FCSE PID Register.

Table 3.126. FCSE PID Register bit functions
Bit rangeField nameFunction
[31:25]FCSE PID

Identifies a specific process for fast context switch.

Holds the ProcID. The reset value is 0.


Reserved. SBZ.

The FCSE PID Register provides the ProcID for fast context switch memory mappings. The MMU uses the contents of this register to map memory addresses in the range 0-32MB.

Accessing the FCSE PID Register

Table 3.127 shows the results of attempted accesses to the FCSE PID Register for each mode.

Table 3.127. Results of accesses to the FCSE PID Register
Privileged readPrivileged writeUser read or write
Data readData writeUndefined Instruction exception

To access the FCSE PID Register you read or write CP15 with:

  • Opcode_1 set to 0

  • CRn set to c0

  • CRm set to c0

  • Opcode_2 set to 0.

For example:

MRC p15, 0, <Rd>, c13, c0, 0            ; Read FCSE PID Register
MCR p15, 0, <Rd>, c13, c0, 0            ; Write FCSE PID Register

Use of the FCSE PID Register

Reading from the FCSE PID Register returns the value of the process identifier.

Writing the FCSE PID Register updates the process identifier to the value in bits[31:25]. Bits[24:0] Should Be Zero. Writing the register globally flushes the BTAC.

Addresses issued by the ARM1136JF-S processor in the range 0-32MB are translated by the ProcID. Address A becomes A + (ProcID x 32MB). This translated address is used by the MMU. Addresses above 32MB are not translated. The ProcID is a seven-bit field, enabling 128 x 32MB processes to be mapped.


If ProcID is 0, as it is on Reset, then there is a flat mapping between the ARM1136JF-S processor and the MMU.

Figure 3.58 shows how addresses are mapped using CP15 c13.

Figure 3.58. Address mapping using CP15 c13

Figure 3.58. Address mapping using CP15 c13

Changing the ProcID, performing a fast context switch

A fast context switch is performed by writing to CP15 c13 FCSE PID Register. The contents of the TLBs do not have to be flushed after a fast context switch because they still hold valid address tags.

From zero to six instructions after the MCR used to write the ProcID might have been fetched with the old ProcID:

{ProcID = 0}
MOV R0, #1                     ; Fetched with ProcID = 0
MCR p15,0,R0,c13,c0,0          ; Fetched with ProcID = 0
A0    (any instruction)        ; Fetched with ProcID = 0/1
A1    (any instruction)        ; Fetched with ProcID = 0/1
A2    (any instruction)        ; Fetched with ProcID = 0/1
A3    (any instruction)        ; Fetched with ProcID = 0/1
A4    (any instruction)        ; Fetched with ProcID = 0/1
A5    (any instruction)        ; Fetched with ProcID = 0/1
A6    (any instruction)        ; Fetched with ProcID = 1


You must not rely on this behavior for future compatibility. You must execute an IMB instruction between changing the ProcID and fetching from locations that are transmitted by the ProcID.