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3.3.44. c15, Cache and Main TLB Master Valid Registers

The purpose of the Cache and Main TLB Master Valid Registers is to hold the state of the Master Valid bits of the instruction and data caches, SmartCaches and main TLBs.

The Master Valid bits enable the Valid bits held in the Instruction and Data Valid RAM for the cache and SmartCache to be masked, so that a single cycle invalidation of the cache can be performed without requiring special resettable RAM cells.

The Cache and Main TLB Master Valid Registers are:

  • In CP15 c15.

  • 32-bit read/write registers. In most cases, the number of registers depends on the cache size:

    • up to eight Instruction Cache Master Valid Registers, depending on the instruction cache size

    • up to eight Instruction SmartCache Master Valid Registers, depending on the instruction SmartCache size

    • up to eight Data Cache Master Valid Registers, depending on the data cache size

    • up to eight Data SmartCache Master Valid Registers, depending on the data SmartCache size

    • two Main TLB Master Valid Registers.

  • Accessible in privileged mode only.

Figure 3.68 shows the arrangement of the CP15 Cache and Main TLB Master Valid Registers.

Figure 3.68. Cache and Main TLB Master Valid Registers

Figure 3.68. Cache and Main TLB Master Valid Registers

Table 3.151 shows the instructions used to access the Cache and Main TLB Master Valid Registers.

Table 3.151. Cache debug CP15 operations
FunctionInstruction
Read Instruction Cache Master Valid RegisterMRC p15, 3, <Rd>, c15, c8, <Register Number>
Write Instruction Cache Master Valid RegisterMCR p15, 3, <Rd>, c15, c8, <Register Number>
Read Instruction SmartCache Master Valid RegisterMRC p15, 3, <Rd>, c15, c10, <Register Number>
Write Instruction SmartCache Master Valid RegisterMCR p15, 3, <Rd>, c15, c10, <Register Number>
Read Data Cache Master Valid RegisterMRC p15, 3, <Rd>, c15, c12, <Register Number>
Write Data Cache Master Valid RegisterMCR p15, 3, <Rd>, c15, c12, <Register Number>
Read Data SmartCache Master Valid RegisterMRC p15, 3, <Rd>, c15, c14, <Register Number>
Write Data SmartCache Master Valid RegisterMCR p15, 3, <Rd>, c15, c14, <Register Number>
Read Main TLB Master Valid RegisterMRC p15, 5, <Rd>, c15, c14, <Register Number>
Write Main TLB Master Valid RegisterMCR p15, 5, <Rd>, c15, c14, Register Number>

The cache and Main TLB Master Valid Registers are summarized in Table 3.152.

Table 3.152. Cache and Main TLB Master Valid Registers summary
RegisterCRm[a]

Number[b]

of registers

Description
Instruction Cache Master Valid Registerc88See Instruction Cache and Instruction SmartCache Master Valid Registers
Instruction SmartCache Master Valid Registerc108
Data Cache Master Valid Registerc128See Data Cache and Data SmartCache Master Valid Registers
Data SmartCache Master Valid Registerc148
Main TLB Master Valid Registerc142See Main TLB Master Valid Registers

[a] See Figure 3.68 for the complete access functions for each register.

[b] There are always two Main TLB Master Valid Registers. The number of Instruction and Data Cache and SmartCache Master Valid Registers depends on the cache sizes, and the numbers given here are the maximum numbers possible.


Instruction Cache and Instruction SmartCache Master Valid Registers

The purpose of the Instruction Cache and Instruction SmartCache Master Valid Registers is to permit the master valid bits for the instruction cache and the instruction SmartCache to be saved and restored. The reasons you might want to do this are:

  • to save the cache master valid bits immediately before entering Dormant mode, and to restore the cache master valid bits on leaving Dormant mode

  • for debug purposes.

The Instruction Cache and Instruction SmartCache Master Valid Registers are:

  • in CP15 c15

  • 32-bit read/write registers

  • accessible in privileged mode only.

The number of Instruction Cache Master Valid Registers implemented depends on the size of the instruction cache, and the number of Instruction SmartCache Master Valid Registers implemented depends on the size of the instruction SmartCache. There is one master valid bit for each 8 cache lines, or for each 8 SmartCache lines:

For example, there are 64 master valid bits for a 16KB cache or SmartCache. Each Master Valid Register holds 32 master valid bits. In this way, the total number of master valid bits determines the number of Master Valid Registers.

For the Instruction Cache and Instruction SmartCache Master Valid Registers:

  • the maximum cache or SmartCache size of 64KB gives 256 master valid bits, requiring eight Master Valid Registers

  • the Master Valid Registers number up from 0

  • the master valid bits fill the registers from the LSB of the Master Valid Register 0

  • reads of unimplemented master valid bits are Unpredictable, and writes to unimplemented bits are Should Be Zero or Preserved (SBZP)

  • the reset value of all Master Valid Registers is 0.

Accessing the Instruction Cache and Instruction SmartCache Master Valid Registers

Table 3.153 shows the results of attempted accesses to the Instruction Cache and Instruction SmartCache Master Valid Registers for each mode.

Table 3.153. Results of accesses to the Instruction Cache and Instruction SmartCache Master Valid Registers
Privileged readPrivileged writeUser read or write
Data readData writeUndefined Instruction exception

To access the Instruction Cache and Instruction SmartCache Master Valid Registers you read or write CP15 with:

  • Opcode_1 set to 3

  • CRn set to c15

  • CRm set to:

    • c8 to access the Instruction Cache Master Valid Registers

    • c10 to access the Instruction SmartCache Master Valid Registers

  • Opcode_2 set to the number of the Master Valid Registers you want to access. The numbering of the registers was described earlier. The value of Opcode_2 is always in the range 0 to 7.

For example:

                MRC p15, 3, <Rd>, c15, c8, 1     ; Read Instruction Cache Master Valid Register 1
                MCR p15, 3, <Rd>, c15, c8, 1     ; Write Instruction Cache Master Valid Register 1
                MRC p15, 3, <Rd>, c15, c10, 0    ; Read Instruction SmartCache Master Valid Register 0
                MCR p15, 3, <Rd>, c15, c10, 0    ; Write Instruction SmartCache Master Valid Register 0

The command examples show accesses to Instruction Cache Master Valid Register 1 and to Instruction SmartCache Master Valid Register 0. The general forms of the instructions are as shown, with <CRm> set to c8 or c10:

 MRC p15, 3, <Rd>, c15, <CRm>, <Register Number> ; Read Instruction (Smart)Cache Master Valid Register
 MCR p15, 3, <Rd>, c15, <CRm>, <Register Number> ; Write Instruction (Smart)Cache Master Valid Register

Data Cache and Data SmartCache Master Valid Registers

The purpose of the Data Cache and Data SmartCache Master Valid Registers is to permit the master valid bits for the data cache and the data SmartCache to be saved and restored. The reasons you might want to do this are:

  • to save the cache master valid bits immediately before entering Dormant mode, and to restore the cache master valid bits on leaving Dormant mode

  • for debug purposes.

The Data Cache and Data SmartCache Master Valid Registers are:

  • in CP15 c15

  • 32-bit read/write registers

  • accessible in privileged mode only.

The number of Data Cache Master Valid Registers implemented depends on the size of the data cache, and the number of Data SmartCache Master Valid Registers implemented depends on the size of the data SmartCache. There is one master valid bit for each 8 cache lines, or for each 8 SmartCache lines:

For example, there are 64 master valid bits for a 16KB cache or SmartCache. Each Master Valid Register holds 32 master valid bits. In this way, the total number of master valid bits determines the number of Master Valid Registers.

For the Data Cache and Data SmartCache Master Valid Registers:

  • the maximum cache or SmartCache size of 64KB gives 256 master valid bits, requiring eight Master Valid Registers

  • the Master Valid Registers number up from 0

  • the master valid bits fill the registers from the LSB of the Master Valid Register 0

  • reads of unimplemented master valid bits are Unpredictable, and writes to unimplemented bits are Should Be Zero or Preserved (SBZP)

  • the reset value of all Master Valid Registers is 0.

Accessing the Data Cache and Data SmartCache Master Valid Registers

Table 3.153 shows the results of attempted accesses to the Data Cache and Data SmartCache Master Valid Registers for each mode.

Table 3.154. Results of accesses to the Data Cache and Data SmartCache Master Valid Registers
Privileged readPrivileged writeUser read or write
Data readData writeUndefined Instruction exception

To access the Data Cache and Data SmartCache Master Valid Registers you read or write CP15 with:

  • Opcode_1 set to 3

  • CRn set to c15

  • CRm set to:

    • c12 to access the Data Cache Master Valid Registers

    • c14 to access the Data SmartCache Master Valid Registers

  • Opcode_2 set to the number of the Master Valid Registers you want to access. The numbering of the registers was described earlier. The value of Opcode_2 is always in the range 0 to 7.

For example:

                      MRC p15, 3, <Rd>, c15, c12, 2     ; Read Data Cache Master Valid Register 2
                      MCR p15, 3, <Rd>, c15, c12, 2     ; Write Data Cache Master Valid Register 2
                      MRC p15, 3, <Rd>, c15, c14, 1     ; Read Data SmartCache Master Valid Register 1
                      MCR p15, 3, <Rd>, c15, c14, 1     ; Write Data SmartCache Master Valid Register 1

The command examples show accesses to Data Cache Master Valid Register 2 and to Data SmartCache Master Valid Register 1. The general forms of the instructions are as shown, with <CRm> set to c12 or c14:

       MRC p15, 3, <Rd>, c15, <CRm>, <Register Number>  ; Read Data (Smart)Cache Master Valid Register
       MCR p15, 3, <Rd>, c15, <CRm>, <Register Number>  ; Write Data (Smart)Cache Master Valid Register

Main TLB Master Valid Registers

The purpose of the Main TLB Master Valid Registers is to permit the master valid bits for the main TLB to be saved and restored. The reasons you might want to do this are:

  • to save the main TLB master valid bits immediately before entering Dormant mode, and to restore the main TLB master valid bits on leaving Dormant mode

  • for debug purposes.

Note

Although you can safely read the Main TLB Master Valid Registers to read the main TLB master valid bits, writing the Main TLB Master Valid Registers to modify the values of these bits can be Unpredictable. You must only write to the Main TLB Master Valid Registers when the cache and main TLB are disabled, and you must only write back the values which you have previously read from the Main TLB Master Valid Registers.

The Main TLB Master Valid Registers are:

  • in CP15 c15

  • two 32-bit read/write registers

  • accessible in privileged mode only.

Accessing the Main TLB Master Valid Registers

Table 3.153 shows the results of attempted accesses to the Main TLB Master Valid Registers for each mode.

Table 3.155. Results of accesses to the Main TLB Master Valid Registers
Privileged readPrivileged writeUser read or write
Data readData writeUndefined Instruction exception

To access the Main TLB Master Valid Registers you read or write CP15 with:

  • Opcode_1 set to 5

  • CRn set to c15

  • CRm set to c14

  • Opcode_2 set to the number of the Main TLB Master Valid Register you want to access. This will be 0 or 1.

For example:

                            MRC p15, 5, <Rd>, c15, c14, 0     ; Read Main TLB Master Valid Register 0
                            MCR p15, 5, <Rd>, c15, c14, 1     ; Write Main TLB Master Valid Register 1