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3.3.43. c15, Cache debug operations registers

The purpose of the cache debug operations registers is to provide debug access to cache operations.

The cache debug operations registers are:

  • In CP15 c15.

  • Six 32-bit registers. Two of these are read-only registers, three are write-only, and one is read/write:

    • the Data Debug Cache Register (read-only)

    • the Instruction Debug Cache Register (read-only)

    • the Data Tag RAM Read Operation Register (write-only)

    • the Instruction Tag RAM Read Operation Register (write-only)

    • the Instruction Cache Data RAM Read Operation Register (write-only)

    • the Cache Debug Control Register (read/write).

  • Accessible in privileged mode only.

Figure 3.63 shows the arrangement of the CP15 cache debug operations registers.

Figure 3.63. Cache debug operations registers

Figure 3.63. Cache debug operations registers

Table 3.145 shows the instructions used to access the cache debug operations registers, and the format of the data supplied to or returned by the accesses.

Table 3.145. Cache debug CP15 operations
FunctionDataInstruction
Read Debug Data Cache RegisterDataMRC p15, 3, <Rd>, c15, c0, 0
Read Debug Instruction Cache RegisterDataMRC p15, 3, <Rd>, c15, c0, 1
Write Data Tag RAM Read Operation RegisterSet/WayMCR p15, 3, <Rd>, c15, c2, 0
Write Instruction Tag RAM Read Operation RegisterSet/WayMCR p15, 3, <Rd>, c15, c2, 1
Write Instruction Cache Data RAM Read Operation RegisterSet/Way/WordMCR p15, 3, <Rd>, c15, c4, 1
Write Cache Debug Control RegisterDataMCR p15, 7, <Rd>, c15, c0, 0
Read Cache Debug Control RegisterDataMRC p15, 7, <Rd>, c15, c0, 0

For debug operations, the cache refill operations can be disabled, while keeping the caches themselves enabled. This enables the debugger to access the system without unsettling the state of the processor. You can use the Cache Debug Control Register to disable the cache refill operations.

c15, Cache Debug Control Register

The purpose of the Cache Debug Control Register is to control cache debug operations. The register is included in the registers listed under c15, Cache debug operations registers.

Figure 3.64 shows the arrangement of bits in the Cache Debug Control Register.

Figure 3.64. Cache Debug Control Register format

Figure 3.64. Cache Debug Control Register format

Table 3.146 shows the bit functions of the Cache Debug Control Register.

Table 3.146. Cache Debug Control Register bit functions
Bit rangeField nameDescription
[31:3]-UNP/SBZ.
[2]WT

Write-Through enable flag:

1 = force write-through behavior for regions marked as write-back.

0 = do not force write-through for regions marked as write-back (normal operation).

The reset value is 0.

[1]IL

Instruction cache Linefill disable flag:

1 = Instruction Cache linefill disabled.

0 = cache linefill enabled (normal operation). This is the reset value.

[0]DL

Data cache Linefill disable flag:

1 = Data Cache linefill disabled.

0 = linefill enabled (normal operation). This is the reset value.


Accessing the Cache Debug Control Register

Table 3.147 shows the results of attempted accesses to the Cache Debug Control Register for each mode.

Table 3.147. Results of accesses to the Cache Debug Control Register
Privileged readPrivileged writeUser read or write
Data readData writeUndefined Instruction exception

To access the Cache Debug Control Register you read or write CP15 with:

  • Opcode_1 set to 7

  • CRn set to c15

  • CRm set to c0

  • Opcode_2 set to 0.

For example:

MRC p15, 7, <Rd>, c15, c0, 0            ; Read cache debug control register
MCR p15, 7, <Rd>, c15, c0, 0            ; Write cache debug control register

c15, Instruction and Data Debug Cache Registers

The purpose of the Debug Cache Registers is to allow data to be read from the instruction and data caches, for debug purposes.

The Instruction and Data Debug Cache Registers are:

  • in CP15 c15

  • two 32-bit read-only registers:

    • the Data Debug Cache Register

    • the Instruction Debug Cache Register

  • accessible in privileged mode only.

Figure 3.65 shows the arrangement of bits in the Instruction and Data Debug Cache Registers.

Figure 3.65. Instruction and Data Debug Cache Register format

Figure 3.65. Instruction and Data Debug Cache
Register format

For the Instruction Cache, the dirty bits are returned as 0.

As shown in Figure 3.65, the formation of the Tag address depends on the cache way size. The returned address consists of Tag RAM contents data, and possibly some Tag Index data. This is described more fully in Table 3.148.

Table 3.148. Construction of the Tag address
Cache way sizeDebug Cache Register bits returned, as part of Tag address
Tag RAM contentsTag Index
4KB or largerBits[31:12]Bits[11:10]
2KBBits[31:11]Bit[10]
1KBBits[31:10]-

Constructing the Tag address in this way ensures that the data format returned is consistent regardless of cache size.

Accessing the Instruction and Data Debug Cache Registers

Table 3.149 shows the results of attempted accesses to the Instruction and Data Debug Cache Registers for each mode.

Table 3.149. Results of accesses to the Instruction and Data Debug Cache Registers
Privileged readPrivileged writeUser read or write
Data readUndefined Instruction exceptionUndefined Instruction exception

To access the Instruction and Data Debug Cache Registers you read CP15 with:

  • Opcode_1 set to 3

  • CRn set to c15

  • CRm set to c0

  • Opcode_2 set to select the Debug Cache Register you want to read:

    • Opcode_2 = 0 for the Data Debug Cache Register

    • Opcode_2 = 1 for the Instruction Debug Cache Register.

For example:

MRC p15, 3, <Rd>, c15, c0, 0            ; Read Data Debug Cache Register
MRC p15, 3, <Rd>, c15, c0, 1            ; Read Instruction Debug Cache Register
Using the Instruction and Data Debug Cache Registers

Reading one of these registers reads a single entry from the instruction or data cache. Usually, the debugger will do this immediately after performing one of the following, by using the appropriate MCR operations:

  • Write to the Data Tag RAM Read Operation Register, to transfer Way and Set information to the data cache. This causes a read of this word in the data Tag RAM into the Data Debug Cache Register.

  • Write to the Instruction Tag RAM Read Operation Register, to transfer Way and Set information to the instruction cache. This causes a read of this word in the instruction Tag RAM into the Instruction Debug Cache Register.

  • Write to the Instruction Cache Data RAM Read Operation Register, to transfer Set, Way and word information to the instruction cache. This causes a read of this word in the instruction cache into the Instruction Debug Cache Register.

Table 3.145 lists the MCR instructions required for each of these operations, and the format of the Read Operation Register data is described in The Read Operation Registers.

The MCR operation is then followed by an MRC operation to read the appropriate Debug Cache Register.

The debugger can use the addresses generated from the Tag to access memory, including the cache.

For SmartCache debug:

  • the base address register can be read to determine the addresses that are covered by the SmartCache

  • linefill operation must be disabled, using the Cache Debug Control Register, to avoid the process of reading data for debug purposes bringing data into the SmartCache.

The Read Operation Registers

The purpose of the Read Operation Registers is to permit a debugger to cause a Tag RAM or data RAM read operation, as described in Using the Instruction and Data Debug Cache Registers.

The Read Operation Registers are:

  • in CP15 c15

  • three 32 bit write-only registers:

    • the Data Tag RAM Read Operation Register

    • the Instruction Tag RAM Read Operation Register

    • the Instruction Cache Data RAM Read Operation Register

  • accessible in privileged mode only.

The Instruction Cache Data RAM Read Operation Register format

When you write to the Instruction Cache Data RAM Read Operation Register you have to provide Set, Way and Word data. The arrangement of bits in the register is shown in Figure 3.66.

Figure 3.66. Instruction Cache Data RAM Read Operation Register format

Figure 3.66. Instruction Cache Data RAM Read Operation
Register format

In this register format:

  • A = log2(Associativity)    rounded up to the next integer

  • S = log2(N Set)

Associativity and N set are cache size parameters, and can be found in the Cache Type register. For more information, see c0, Cache Type Register.

The Data and Instruction Tag RAM Read Operation Register formats

The Tag RAM Read Operations register require Way and Set data. The arrangement of bits in the register is shown in Figure 3.67. The A and S values are defined in the same way as they are for Figure 3.66.

Figure 3.67. Tag RAM Read Operation Register format

Figure 3.67. Tag RAM Read Operation Register format

Accessing the Read Operation Registers

Table 3.150 shows the results of attempted accesses to the Read Operation Registers for each mode.

Table 3.150. Results of accesses to the Instruction and Data Debug Cache Registers
Privileged readPrivileged writeUser read or write
Undefined Instruction exceptionData readUndefined Instruction exception

To access the Read Operation Registers you write CP15 with:

  • Opcode_1 set to 3

  • CRn set to c15

  • CRm set to select between the Tag RAM and the Instruction Cache Data RAM Read Operations Registers:

    • CRm = c2 for the Tag RAM Read Operation Registers

    • CRm = c4 for the Instruction Cache Data RAM Read Operations Register

  • Opcode_2 set to select the Read Operation Registers you want to access:

    • Opcode_2 = 0 for the Data Tag RAM Read Operation Register

    • Opcode_2 = 1 for the Instruction Tag RAM Read Operation Register

    • Opcode_2 = 1 for the Instruction Cache Data RAM Read Operations Register.

For example:

        MCR p15, 3, <Rd>, c15, c2, 0        ; Write Data Tag RAM Read Operation Register
        MCR p15, 3, <Rd>, c15, c2, 1        ; Write Instruction Tag RAM Read Operation Register
        MCR p15, 3, <Rd>, c15, c4, 1        ; Write Instruction Cache Data RAM Read Operations Register