The purpose of the Count Register 0 is to count instances of the event that is specified in the Performance Monitor Control Register.
The Count Register 0:
is in CP15 c15
is a 32-bit read/write register
is accessible only in privileged mode
counts up, and can trigger an interrupt on overflow.
Count Register 0 bits[31:0] contain the count value. The reset value is 0.
Table 3.143 shows the results of attempted accesses to the Count Register 0 for each mode.
|Privileged read||Privileged write||User read or write|
|Data read||Data write||Undefined Instruction exception|
To access Count Register 0 you read or write CP15 with:
Opcode_1 set to 0
CRn set to c15
CRm set to c12
Opcode_2 set to 2.
MRC p15, 0, <Rd>, c15, c12, 2 ; Read Count Register 0
MCR p15, 0, <Rd>, c15, c12, 2 ; Write Count Register 0
You can use Count Register 0 in conjunction with the Performance Monitor Control Register, the Cycle Count Register, and Count Register 1 to provide a variety of useful metrics that enable you to optimize system performance.
The Performance Monitor Control Register can be used to:
set Count Register 0 to zero
specify the event which increments Count Register 0
enable the generation of an interrupt when Count Register 0 overflows.
From release r1p0, this register is not incremented while the processor is in Halting debug-mode.