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3.3.40. c15, Cycle Counter Register (CCNT)

The purpose of the Cycle Counter Register is to count the core clock cycles.

The Cycle Counter Register:

  • is in CP15 c15

  • is a 32-bit read/write register

  • is accessible only in privileged mode

  • counts up, and can trigger an interrupt on overflow.

The Cycle Counter Register bits[31:0] contain the count value. The value in the register is Unpredictable at Reset.

Accessing the Cycle Counter Register

Table 3.142 shows the results of attempted accesses to the Cycle Count Register for each mode.

Table 3.142. Results of accesses to the Cycle Count Register
Privileged readPrivileged writeUser read or write
Data readData writeUndefined Instruction exception

To access the Cycle Counter Register you read or write CP15 with:

  • Opcode_1 set to 0

  • CRn set to c15

  • CRm set to c12

  • Opcode_2 set to 1.

For example:

MRC p15, 0, <Rd>, c15, c12, 1               ; Read Cycle Counter Register
MCR p15, 0, <Rd>, c15, c12, 1               ; Write Cycle Counter Register

Using the Cycle Counter Register

You can use the Cycle Counter Register in conjunction with the Performance Monitor Control Register and the two Counter Registers to provide a variety of useful metrics that enable you to optimize system performance.

The Performance Monitor Control Register can be used to:

  • set the Cycle Counter Register to zero

  • configure the Cycle Counter Register to count every 64th clock cycle

  • enable the generation of an interrupt when the Cycle Counter Register overflows.

Note

From release r1p0, the Cycle Counter Register is not incremented while the processor is in Halting debug-mode.