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3.3.38. c15, Memory remap registers

The purpose of the memory remap registers is to remap memory region types. The remapping takes place on the outputs of the MMU, and overrides the settings specified in the MMU page tables, or the default behavior when the MMU is disabled.

You can use these registers to remap both Inner and Outer attributes.

The c15 memory remap registers are:

  • in CP15 c15

  • four 32-bit read/write registers

    • the Opcode_2 value controls which memory remap registers is accessed

  • accessible in privileged modes only.

The four memory remap registers are:

  • the Data Memory Remap Register, accessed when Opcode_2 = 0

  • the Instruction Memory Remap Register, accessed when Opcode_2 = 1

  • the DMA Memory Remap Register, accessed when Opcode_2 = 2

  • the Peripheral Port Memory Remap Register, accessed when Opcode_2 = 4.

Note

In addition to the c15 memory remap registers, additional memory remapping can occur because of remapping of the memory region attributes encoded by the TEX[2:0], C, and B bits in the MMU page tables. See c10, TEX remap registers for more information.

Format of the Instruction, Data and DMA Memory Remap Registers

Figure 3.60 shows the arrangement of bits in these registers.

Figure 3.60. Instruction, Data, and DMA Memory Remap Registers format

Figure 3.60. Instruction, Data, and DMA Memory
Remap Registers format

Table 3.131 shows the bit functions of the Instruction, Data, and DMA Memory Remap Registers.

Table 3.131. Instruction, Data and DMA Memory Remap Register bit functions
Bit rangeRemapped regionPermitted encodingsReset value
[31:25]SBZ/UNP--
[24:23]Outer Write-Back, No Write on AllocateSee Table 3.132.b11
[22:21]Outer Write-Through, No Write on Allocateb10
[20:19]Outer Write-Back, Write on Allocateb01
[18:17]Outer Noncacheableb00
[16]Shared attribute remapping if Shared bit = 1 (shared)n/ab1
[15]Shared attribute remapping if Shared bit = 0 (not shared)n/ab0
[14:12]Inner Write-BackSee Table 3.133.b111
[11:9]Inner Write-Throughb110
[8:6]Deviceb011
[5:3]Strongly Orderedb001
[2:0]Inner Noncacheableb000

The reset value for each field ensures that by default no remapping occurs.

Table 3.132 show the encoding used for Outer regions.

Table 3.132. Memory remap registers - outer region remap encoding
Outer regionEncoding
Noncacheableb00
Write-Back, Write on Allocateb01
Write-Through, No Write on Allocateb10
Write-Back, No Write on Allocateb11

Table 3.133 shows the encoding used for Inner regions.

Table 3.133. Memory remap registers - inner region remap encoding
Inner regionEncoding
Noncacheableb000
Strongly Orderedb001
Reservedb010
Deviceb011
Reservedb100
Reservedb101
Write-Throughb110
Write-Backb111

Format of the Peripheral Port Memory Remap Register

Figure 3.61 shows the arrangement of bits in the register.

Figure 3.61. Peripheral Port Memory Remap Register format

Figure 3.61. Peripheral Port Memory Remap Register
format

Table 3.134 shows the shows the bit functions of the Peripheral Port Memory Remap Register.

Table 3.134. Peripheral Port Memory Remap Register bit functions
BitsField nameFunction
[31:12]Base Address

Gives the physical base address of the region of memory to be remapped to the peripheral port. If the Peripheral Port Memory Remap Register is used while the MMU is disabled, the virtual base address is equal to the physical base address that is used.

The Base Address is assumed to be aligned to the size of the remapped region. Any bits in the range [(log2(Region size)-1):12] are ignored.

The Base Address is 0 at Reset.

[11:5]UNP/SBZ-
[4:0]Size

Indicates the size of the memory region that is to be remapped to be used by the peripheral port.

Size is 0 at Reset, indicating that no remapping is to take place.

Table 3.135 shows the region size encoding of the Size field.


Table 3.135 shows the encoding of the Size field for different remap region sizes.

Table 3.135. Peripheral Port Memory Remap Register Size field encoding
Size fieldRegion Size
b00000 0KB
b00011 4KB
b00100 8KB
b00101 16KB
b00110 32KB
b00111 64KB
b01000 128KB
b01001 256KB
b01010 512KB
b01011 1MB
b011002MB
b011014MB
b011108MB
b0111116MB
b1000032MB
b1000164MB
b10010128MB
b10011256MB
b10100512MB
b101011GB
b101102GB

Accessing the memory remap registers

Table 3.127 shows the results of attempted accesses to the memory remap registers for each mode.

Table 3.136. Results of accesses to the Memory Remap Registers
Privileged readPrivileged writeUser read or write
Data readData writeUndefined Instruction exception

To access the memory remap registers you read or write CP15 with:

  • Opcode_1 set to 0

  • CRn set to c15

  • CRm set to c2

  • Opcode_2 set to indicate the required memory remap register:

    • Opcode_2 = 0 for the Data Memory Remap Register

    • Opcode_2 = 1 for the Instruction Memory Remap Register

    • Opcode_2 = 2 for the DMA Memory Remap Register

    • Opcode_2 = 4 for the Peripheral Port Memory Remap Register.

For example:

MRC p15, 0, <Rd>, c15, c2, 0       ; Read the Data Memory Remap Register
MCR p15, 0, <Rd>, c15, c2, 0       ; Write the Data Memory Remap Register
MRC p15, 0, <Rd>, c15, c2, 1       ; Read the Instruction Memory Remap Register
MCR p15, 0, <Rd>, c15, c2, 1       ; Write the Instruction Memory Remap Register
MRC p15, 0, <Rd>, c15, c2, 2       ; Read the DMA Memory Remap Register
MCR p15, 0, <Rd>, c15, c2, 2       ; Write the DMA Memory Remap Register
MRC p15, 0, <Rd>, c15, c2, 4       ; Read Peripheral Port Memory Remap Register
MCR p15, 0, <Rd>, c15, c2, 4       ; Write Peripheral Port Memory Remap Register

Using the Instruction, Data and DMA Memory Remap Registers

Each memory region register is split into two parts covering the Inner and Outer attributes respectively. The Inner attributes are covered by five three bit fields, and the Outer attributes are covered by four two bit fields.

The Shared bit can also be remapped. If the Shared bit as read from the TLB or page tables is 0, then it is remapped to bit 15 of this register. If the Shared bit as read from the TLB or page tables is 1, then it is remapped to bit 16 of this register.

Remapping when the MMU is disabled

Table 3.137 shows the default values of the memory regions, or region types, when the MMU is disabled.

Table 3.137. Default memory regions when MMU is disabled
Condition[a]Default region type, MMU disabled
Data Cache enabledData, Strongly Ordered
Data Cache disabled Data, Strongly Ordered
Instruction Cache enabledInstruction, Write-Through
Instruction Cache disabledInstruction, Strongly Ordered

[a] As set in the Control Register, see c1, Control Register.

      Bit[12], the I bit, enables or disables the Instruction Cache,

      Bit[2], the C bit, enables or disables the Data Cache.


These region types apply before any remapping. However, any remappings specified in the Remap Registers will be applied to these settings. For example, when the Instruction Cache is enabled, the final region type will depend on any remapping of Write-Through that is specified in the Instruction Region Remap Register.

This remapping enables different mappings to be selected with the MMU disabled, that cannot be done using only the I, C, and M bits in CP15 c1.

Using the Peripheral Port Memory Remap Register

You use this register to remap the peripheral port.

The peripheral port is accessed by memory locations whose page table attributes are Non-Shared Device. You can program a region of memory to be remapped to being Non-Shared Device while the MMU is disabled to provide access to the peripheral port when the MMU is disabled. In addition, the same mechanism will override the page table entries, providing an additional mechanism for accessing the peripheral port. This mechanism is suitable for operating systems where access to the page table formats is not readily available.

The use of the remapping of the peripheral port will change the memory region used for those memory locations that are remapped to be Non-Shared Device, regardless of what has been programmed in the page tables.

If the region of memory mapped by this mechanism overlaps with the regions of memory that are contained within the TCMs not marked as SmartCache, then the memory locations that are mapped as both TCM and Non-Shared Device are treated as TCM. Therefore, the overlapping region does not access the peripheral port.

If the region of memory mapped by this mechanism overlaps with the regions of memory that are contained within the TCMs marked as SmartCache, then the memory locations that are mapped as both TCM and Non-Shared Device are treated as Non-Shared Device, and the SmartCache functionality is not used enabled for those addresses.

The peripheral port is only used by data accesses. Unaligned accesses and exclusive accesses are not supported by the peripheral port (because they are not supported in Device memory), and attempting to perform such accesses has Unpredictable results when using the peripheral port as a result of the Peripheral Port Memory Remap Register.

Any remapping on Non-Shared Device memory by the Data Memory Remap Register has no effect on regions mapped to Non-Shared Device by the Peripheral Port Memory Remap Register.

To entirely disable the peripheral port, the Peripheral Port Memory Remap Register must be programmed to 0 size and page table entries of type Non-Shared Device must be avoided.