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3.3.45. c15, MMU debug operations overview

Figure 3.69 shows the arrangement of the CP15 registers provided for MMU debug operations. You can also use these registers to read state information before you enter Dormant mode, and to restore state information on returning from Dormant mode.

Figure 3.69. Registers for MMU debug operations

Figure 3.69. Registers for MMU debug operations

These registers are described in the following sections:

MMU debugging describes using these registers to perform MMU debug.

c15, Instruction MicroTLB and Data MicroTLB Index Registers

The purpose of the MicroTLB Index Registers is to provide access to the Instruction and Data MicroTLB entries.

The MicroTLB Index Registers are:

  • in CP15 c15

  • two 32 bit read/write registers

    • the Instruction MicroTLB Index Register

    • the Data MicroTLB Index Register

  • accessible in privileged mode only.

Figure 3.70 shows the arrangement of bits in the registers.

Figure 3.70. MicroTLB Index Register format

Figure 3.70. MicroTLB Index Register format

Table 3.156 shows the bit functions of the MicroTLB Index Registers.

Table 3.156. MicroTLB Index Registers bit functions
Bit rangeField name

Function

[31:4] SBZ/UNP.
[3:0]Index

Indicates which entry in the MicroTLB is accessed.

Permitted values are b0000 to b1010, decimal 0 to 10.


Note

MicroTLB index values greater than 10 do not access any MicroTLB entry.

Accessing the MicroTLB Index Registers

Table 3.157 shows the results of attempted accesses to the Instruction MicroTLB and Data MicroTLB Index Registers for each mode.

Table 3.157. Results of accesses to the Instruction MicroTLB and Data MicroTLB Index Registers
Privileged readPrivileged writeUser read or write
Data readData writeUndefined Instruction exception

To access the MicroTLB Index Registers you read or write CP15 with:

  • Opcode_1 set to 5

  • CRn set to c15

  • CRm set to c4

  • Opcode_2 set to:

    • 0 to access the Data MicroTLB Index Register

    • 1 to access the Instruction MicroTLB Index Register.

For example:

MRC p15, 5, <Rd>, c15, c4, 0         ; Read Data MicroTLB Index Register
MCR p15, 5, <Rd>, c15, c4, 0         ; Write Data MicroTLB Index Register
MRC p15, 5, <Rd>, c15, c4, 1         ; Read Instruction MicroTLB Index Register
MCR p15, 5, <Rd>, c15, c4, 1         ; Write Instruction MicroTLB Index Register

See MicroTLB debug for a description of using the MicroTLB Index Registers for debugging the MicroTLBs.

c15, Main TLB Entry Registers (Main TLB Index Registers)

The purpose of the Main Entry Registers is to provide access to main TLB read and write entries. The registers are also referred to as the Main TLB Index Registers.

The Main TLB Entry Registers are:

  • in CP15 c15

  • two 32 bit write-only registers

    • the Read Main TLB Entry Register

    • the Write Main TLB Entry Register

  • accessible in privileged mode only.

Figure 3.71 shows the arrangement of bits in the registers.

Figure 3.71. Main TLB Index Register format

Figure 3.71. Main TLB Index Register format

Table 3.158 shows the bit functions of the Main TLB Entry Registers.

Table 3.158. Main TLB Entry Registers bit functions
Bit rangeNameMeaning
[31]L

Lockable region. Indicates whether the index refers to the lockable region or the set-associative region:

0 = Index refers to the set-associative region

1 = Index refers to the lockable region.

[30:6]-SBZ.
[5:0]Index

Indicates which entry in the main TLB is accessed. The meaning of this field depends on the setting of the L bit:

L = 0

Index[5] indicates which Way of the main TLB set-associative region is being accessed.

Index[4:0] indexes the Set of the RAM.

L = 1

Index[5:3] SBZ.

Index[2:0] indicates which entry in the lockable region is being accessed.


Accessing the Main TLB Entry Registers

Table 3.159 shows the results of attempted accesses to the Main TLB Entry Registers for each mode.

Table 3.159. Results of accesses to the Main TLB Entry Registers
Privileged readPrivileged writeUser read or write
Undefined Instruction exceptionData writeUndefined Instruction exception

To access the Main TLB Entry Registers you write CP15 with:

  • Opcode_1 set to 5

  • CRn set to c15

  • CRm set to c4

  • Opcode_2 set to:

    • 2 to access the Read Main TLB Entry Register

    • 4 to access the Write Main TLB Entry Register.

For example:

MCR p15, 5, <Rd>, c15, c4, 2          ; Write to Read Main TLB Entry Register
MCR p15, 5, <Rd>, c15, c4, 4          ; Write to Write Main TLB Entry Register

See Main TLB debug for a description of using the Main TLB Entry Registers for debugging the main TLBs.