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3.3.39. c15, Performance Monitor Control Register (PMNC)

The purpose of the Performance Monitor Control Register is to control the operation of:

  • the Cycle Counter Register (CCNT)

  • the Count Register 0 (PMN0)

  • the Count Register 1 (PMN1).

The Performance Monitor Control Register is:

  • in CP15 c15

  • a 32-bit read/write register

  • accessible in privileged mode only.

Figure 3.62 shows the arrangement of bits in the register.

Figure 3.62. Performance Monitor Control Register format

Figure 3.62. Performance Monitor Control Register
format

Table 3.138 shows the bit functions of the Performance Monitor Control Register.

Table 3.138. Performance Monitor Control Register bit functions
Bit rangeField nameFunction
[31:28]-UNP/SBZ.
[27:20] EvtCount0Identifies the source of events for Count Register 0, as defined in Table 3.141.
[19:12] EvtCount1Identifies the source of events for Count Register 1, as defined in Table 3.141.
[11]X

Enable Export of the events to the event bus. This enables an external monitoring block, such as the ETM to trace events:

0 = Export disabled, EVNTBUS held at 0x0. This is the reset value.

1 = Export enabled, EVNTBUS driven by the events.

[10]CCRCycle Count Register overflow flag. See Table 3.139 for the meaning of the flag values.
[9]CR1Count Register 1 overflow flag. See Table 3.139 for the meaning of the flag values.
[8]CR0Count Register 0 overflow flag. See Table 3.139 for the meaning of the flag values.
[7]-UNP/SBZ.
[6]ECC

Enable Cycle Counter interrupt.

0 = Disable interrupt. This is the reset value.

1 = Enable interrupt.

[5]EC1

Enable Counter Register 1 interrupt.

0 = Disable interrupt. This is the reset value.

1 = Enable interrupt.

[4]EC0

Enable Counter Register 0 interrupt.

0 = Disable interrupt. This is the reset value.

1 = Enable interrupt.

[3]D

Cycle count divider:

0 = Cycle Counter Register counts every processor clock cycle.

1 = Cycle Counter Register counts every 64th processor clock cycle.

[2]C

Cycle Counter Register Reset on Write, UNP on Read:

Write 0 = no action

Write 1 = reset the Cycle Counter Register to 0x0.

[1]P

Count Register Reset on Write, UNP on Read:

Write 0 = no action

Write 1 = reset both Count Registers to 0x0.

[0]E

Enable:

0 = all three counters disabled

1 = all three counters enabled.

The PMUIRQ signal can only be cleared when this bit is set to 1. This signal is the mechanism by which a Performance Monitor Unit interrupt is signaled to the core, see Using the Performance Monitor Control Register for more information.


The meaning of the flags in the Performance Monitor Control Register, for read and write operations, are shown in Table 3.139:

Table 3.139. PMNC flag values
Flag valueOn readsOn write
0No overflow has occurred. This is the reset value.No effect.
1An overflow has occurred.Clear this bit.

Accessing the Performance Monitor Control Register

Table 3.140 shows the results of attempted accesses to the Performance Monitor Control Register for each mode.

Table 3.140. Results of accesses to the Performance Monitor Control Register
Privileged readPrivileged writeUser read or write
Data readData writeUndefined Instruction exception

To access the Performance Monitor Control Register you read or write CP15 with:

  • Opcode_1 set to 0

  • CRn set to c15

  • CRm set to c12

  • Opcode_2 set to 0.

For example:

MRC p15, 0, <Rd>, c15, c12, 0       ; Read Performance Monitor Control Register
MCR p15, 0, <Rd>, c15, c12, 0       ; Write Performance Monitor Control Register

Using the Performance Monitor Control Register

The Performance Monitor Control Register:

  • controls which events PMN0 and PMN1 monitor

  • detects which counter overflowed

  • enables and disables interrupt reporting

  • extends CCNT counting by six more bits (cycles between counter rollover = 238)

  • resets all counters to zero

  • enables the entire performance monitoring mechanism.

If an interrupt is generated by this unit, the ARM1136JF-S processor pin PMUIRQ is asserted. This output pin can then be routed to an external interrupt controller for prioritization and masking. This is the only mechanism by which the interrupt is signaled to the core. When asserted, the PMUIRQ signal can only be cleared if bit[0] of the register, the E bit, is HIGH.

There is a delay of three cycles between enabling the counter and the counter starting to count events. In addition, the information used to count events is taken from various pipeline stages. This means that the absolute counts recorded might vary because of pipeline effects. This has a negligible effect except in case where the counters are enabled for a very short time.

Table 3.141 shows the events that can be monitored using the Performance Monitor Control Register.

Table 3.141. Performance monitoring events
Event numberEVNTBUS bit positionEvent definition
0x0[0]Instruction cache miss to a cacheable location requires fetch from external memory.
0x1[1]

Stall because instruction buffer cannot deliver an instruction. This could indicate an Instruction Cache miss or an Instruction MicroTLB miss.

This event occurs every cycle in which the condition is present.

0x2[2]

Stall because of a data dependency.

This event occurs every cycle in which the condition is present.

0x3[3]Instruction MicroTLB miss.
0x4[4]Data MicroTLB miss.
0x5[6:5]Branch instruction executed, branch might or might not have changed program flow.
0x6[7]Branch mis-predicted.
0x7[9:8]Instruction executed.
0x9[10]

Data cache access, not including Cache operations.

This event occurs for each nonsequential access to a cache line, for cacheable locations.

0xA[11]

Data cache access, not including Cache Operations.

This event occurs for each nonsequential access to a cache line, regardless of whether or not the location is cacheable.

0xB[12]Data cache miss, not including Cache Operations.
0xC[13]

Data cache write-back.

This event occurs once for each half line of four words that are written back from the cache.

0xD[15:14]

Software changed the PC.

This event occurs any time the PC is changed by software and there is not a mode change. For example, a MOV instruction with PC as the destination triggers this event.

Executing a SWI from User mode does not trigger this event, because it incurs a mode change.

0xF[16]Main TLB miss.
0x10[17]

Explicit external data access.

This includes Cache Refill, Noncacheable and Write-Through accesses. It does not include Write-Backs, instruction cache line fills, and page table walks.

0x11[18]

Stall because of Load Store Unit request queue being full.

This event occurs each clock cycle in which the condition is met.

A high incidence of this event indicates the BCU is often waiting for transactions to complete on the external bus.

0x12[19]The number of times the Write Buffer was drained because of a Data Synchronization Barrier command or Strongly Ordered operation.
0x20-ETMEXTOUT[0] signal was asserted for a cycle.
0x21-ETMEXTOUT[1] signal was asserted for a cycle.
0x22-If both ETMEXTOUT[0] and ETMEXTOUT[1] signals are asserted then the count is incremented by two.
0xFF-An increment each cycle.
All other values-Reserved. Unpredictable behavior.

In addition to the two counters within ARM1136JF-S processors, each of the events shown in Table 3.141 is available on an external bus, EVNTBUS. You can connect this bus to the ETM unit or other external trace hardware to enable the events to be monitored. If this functionality is not required, you must set the X bit in the Performance Monitor Control Register to the 0.