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3.3.9. c2, Translation Table Base Register 0, TTBR0

The purpose of the Translation Table Base Register 0 is to hold the physical address of the first-level translation table.

You use Translation Table Base Register 0 for process-specific addresses, where each process maintains a separate first-level page table. On a context switch you must modify both Translation Table Base Register 0 and the Translation Table Base Control Register, if appropriate.

The Translation Table Base Register 0 is:

  • in CP15 c2

  • a 32 bit read/write register

  • accessible in privileged mode only.

Figure 3.29 shows the bit functions of the register.

Figure 3.29. Translation Table Base Register 0 format

Figure 3.29. Translation Table Base Register 0
format

Table 3.52 lists the bit functions of the Translation Table Base Register 0.

Table 3.52. Translation Table Base Register 0 field descriptions
BitsNameFunction
[31:(14-N)][a]Translation table base 0Pointer to the level one translation table.
[(13-N):5][a]-UNP/SBZ.
[4:3]RGN

Outer cacheable attributes for page table walking:

b00 = Outer Noncacheable

b01 = Outer Cacheable Write-Back cached, Write Allocate

b10 = Outer Cacheable Write-Through, No Allocate on Write

b11 = Outer Cacheable Write-Back, No Allocate on Write.

[2]-

Reserved, SBZP.

[1]S

Indicates whether the page table walk is to Shared or Non-Shared memory.

0 = Non-Shared. This is the reset value.

1 = Shared.

[0]C

Indicates whether the page table walk is Inner Cacheable or Inner Noncacheable.

0 = Inner noncacheable. This is the reset value.

1 = Inner cacheable.

[a] The value of N is defined in the Translation Table Base Control Register, see c2, Translation Table Base Control Register, TTBCR.


Accessing the Translation Table Base Register 0

Table 3.53 shows the results of attempted accesses to the Translation Table Base Register 0 for each mode.

Table 3.53. Results of accesses to the Translation Table Base Register 0
Privileged readPrivileged writeUser read or write
Data readData writeUndefined Instruction exception

To access the Translation Table Base Register 0 you read or write CP15 with:

  • Opcode_1 set to 0

  • CRn set to c2

  • CRm set to c0

  • Opcode_2 set to 0.

For example:

MRC p15, 0, <Rd>, c2, c0, 0            ; Read Translation Table Base Register 0
MCR p15, 0, <Rd>, c2, c0, 0            ; Write Translation Table Base Register 0

Note

The ARM1136JF-S processor cannot perform a page table walk from level one cache. Therefore, to ensure coherency, when C = 1 you must do one of:

  • store the page tables in Inner Write-Through memory

  • if in Inner Write-Back memory, clean the appropriate cache entries after modification to ensure that they are seen by the hardware page table walking mechanism.