You copied the Doc URL to your clipboard.

3.3.10. c2, Translation Table Base Register 1, TTBR1

The purpose of the Translation Table Base Register 1 is to hold the physical address of the first-level table. Use Translation Table Base Register 1 for operating system and I/O addresses.

Figure 3.30 shows the arrangement of bits in the register.

Figure 3.30. Translation Table Base Register 1 format

Figure 3.30. Translation Table Base Register 1
format

Table 3.54 lists the bit functions of the Translation Table Base Register 1.

Table 3.54. Translation Table Base Register 1 field descriptions
BitsNameFunction
[31:14]Translation table base 1Pointer to the level one translation table.
[13:5]-UNP/SBZ.
[4:3]RGN

Outer cacheable attributes for page table walking:

b00 = Outer Noncacheable

b01 = Outer Cacheable Write-Back cached, Write Allocate

b10 = Outer Cacheable Write-Through, No Allocate on Write

b11 = Outer Cacheable Write-Back, No Allocate on Write.

[2]-

Reserved, SBZP.

[1]S

Indicates whether the page table walk is to Shared or Non-Shared memory.

0 = Non-Shared. This is the reset value.

1 = Shared.

[0]C

Indicates whether the page table walk is Inner Cacheable or Inner Noncacheable.

0 = Inner noncacheable. This is the reset value.

1 = Inner cacheable.

All page table accesses are Outer Cacheable.


Accessing the Translation Table Base Register 1

Table 3.55 shows the results of attempted accesses to the Translation Table Base Register 1 for each mode.

Table 3.55. Results of accesses to the Translation Table Base Register 1
Privileged readPrivileged writeUser read or write
Data readData writeUndefined Instruction exception

You can access Translation Table Base Register 1 by reading or writing CP15 c2 with:

  • Opcode_1 set to 0

  • CRn set to c2

  • CRm set to c0

  • Opcode_2 set to 1.

For example:

MRC p15, 0, <Rd>, c2, c0, 1            ; Read Translation Table Base Register 1
MCR p15, 0, <Rd>, c2, c0, 1            ; Write Translation Table Base Register 1 

Writing to CP15 c2 updates the pointer to the first-level translation table, using the value in bits [31:14] of the register write. Bits [13:5] Should Be Zero.

Translation Table Base Register 1 must reside on a 16KB page boundary.

Note

The ARM1136JF-S processor cannot perform a page table walk from level one cache. Therefore, to ensure coherency, when C = 1 you must do one of:

  • store the page tables in Inner Write-Through memory

  • if in Inner Write-Back memory, clean the appropriate cache entries after modification to ensure that they are seen by the hardware page table walking mechanism.