The purpose of the Instruction Fault Status Register (IFSR) is to hold the source of the last instruction fault. The IFSR indicates the type of access being attempted when an abort occurred.
The Instruction Fault Status Register is:
in CP15 c5
a 32-bit read/write register
accessible in privileged mode only.
Figure 3.34 shows the arrangement of bits in the register.
Table 3.64 shows the bit functions of the Instruction Fault Status Register.
The fault status field bit encodings are shown in Table 3.65.
|b0000||No function, reset value|
|b0010||Debug event fault|
|b0011||Access Flag fault on Section|
|b0101||Translation fault on Section|
|b0110||Access Flag fault on Page|
|b0111||Translation fault on Page|
|b1000||Precise External Abort|
|b1001||Domain fault on Section|
|b1011||Domain fault on Page|
|b1100||External abort on translation, first level|
|b1101||Permission fault on Section|
|b1110||External abort on translation, second level|
|b1111||Permission fault on Page|
[a] Bits[3:0] of the IFSR register.
[b] On the DFST, the corresponding encoding (0b00100) indicates a cache maintenance operation fault. These faults cannot occur on the instruction side.
Table 3.66 shows the results of attempted accesses to the Instruction Fault Status Register for each mode.
|Privileged read||Privileged write||User read or write|
|Data read||Data write||Undefined Instruction exception|
To access the Instruction Fault Status Register you read or write CP15 with:
Opcode_1 set to 0
CRn set to c5
CRm set to c0
Opcode_2 set to 1.
MRC p15, 0, <Rd>, c5, c0, 1 ; Read Instruction Fault Status Register
MCR p15, 0, <Rd>, c5, c0, 1 ; Write Instruction Fault Status Register
Reading CP15 c5 with the Opcode_2 field set to 1 returns the value of the IFSR.
Writing CP15 c5 with the Opcode_2 field set to 1 sets the IFSR to the value of the data written. This is useful for a debugger to restore the value of the IFSR. Bits [31:4] Should Be Zero.