There are two cache lockdown registers:
Data Cache Lockdown Register
Instruction Cache Lockdown Register.
The purpose of the data and instruction cache lockdown registers is to provide a means to lock down the caches and therefore provide some control over pollution that applications might cause. With these registers you can lock down each cache way independently.
The cache lockdown registers are:
in CP15 c9
two 32-bit read/write registers
accessible in privileged mode only.
Figure 3.45 shows the arrangement of bits in these registers.
Table 3.91 shows the bit functions of the Cache Lockdown Registers.
|Bit range||Field name||Function|
|[31:4]||SBO||UNP on reads, SBO on writes.|
|[3:0]||L bit for each cache way|
Locks each cache way individually. The L bits for cache ways 3 to 0 are bits [3:0] respectively. On a line fill to the cache, data is allocated to unlocked cache ways as determined by the standard replacement algorithm. Data is not allocated to locked cache ways.
If a cache way is not implemented, then the L bit for that way is hardwired to 1, and writes to that bit are ignored.
0 indicates that this cache way is not locked. Allocation to this cache way is determined by the standard replacement algorithm. This is the reset state.
1 indicates that this cache way is locked. No allocation is performed to this cache way.
ARM1136JF-S processors only support one method of using cache lockdown registers, called Format C. This is a cache way based scheme that gives a traditional lockdown function to lock critical regions in the cache.
A locking bit for each cache way determines if the normal cache allocation mechanism is able to access that cache way. Bit of the Control Register, the RR bit, controls whether a random or a round-robin cache allocation policy is used, see c1, Control Register for more information.
ARM1136JF-S processors have an associativity of 4. If all ways are locked, the ARM1136JF-S processor behaves as if only ways 3 to 1 are locked and way 0 is unlocked.
Table 3.92 shows the results of attempted accesses to the Cache Lockdown Registers for each mode.
|Privileged read||Privileged write||User read or write|
|Data read||Data write||Undefined Instruction exception|
To access the Cache Lockdown Registers you read or write CP15 with:
Opcode_1 set to 0
CRn set to c9
CRm set to c0
Opcode_2 set to:
0 to access the Data Cache Lockdown Register
1 to access the Instruction Cache Lockdown Register.
MRC p15, 0, <Rd>, c9, c0, 0 ; Read Data Cache Lockdown Register
MCR p15, 0, <Rd>, c9, c0, 0 ; Write Data Cache Lockdown Register
MRC p15, 0, <Rd>, c9, c0, 1 ; Read Instruction Cache Lockdown Register
MCR p15, 0, <Rd>, c9, c0, 1 ; Write Instruction Cache Lockdown Register
The system must only change a cache lockdown register when it is certain that all outstanding accesses that might cause a cache line fill are complete. For this reason, the processor must execute a Data Synchronization Barrier instruction before the cache lockdown register changes, see Accessing the Data Synchronization Barrier operation.
The following procedure for lock down into a data or instruction cache way i, with N cache ways, using Format C, ensures that only the target cache way i is locked down.
This is the architecturally defined method for locking data into caches:
Ensure that no processor exceptions can occur during the execution of this procedure, by disabling interrupts. If this is not possible, all code and data used by any exception handlers that can be called must be treated as code and data prior to step 2.
Ensure that all data used by the following code, apart from the data that is to be locked down, is either:
in an uncacheable area of memory, including the TCM
in an already locked cache way.
Ensure that the data to be locked down is in a Cacheable area of memory.
Ensure that the data to be locked down is not already in the cache, using cache Clean and/or Invalidate instructions as appropriate.
Enable allocation to the target cache way by writing to CP15 c9, with the CRm field set to 0, setting L equal to 0 for bit i and L equal to 1 for all other ways.
Ensure that the memory cache line is loaded into the cache by using an
LDRinstruction to load a word from the memory cache line, for each of the cache lines to be locked down in cache way i.
Write to CP15 c9, CRm = c0, setting L to 1 for bit i and restore all the other bits to the values they had before this routine was started.