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Appendix C. Revisions

This appendix describes the technical changes between released issues of this book.

Table C.1. Differences between issue J and issue K
ChangeLocation
Enhancements to instruction set descriptionsARM1136JF-S instruction sets summaries
Updated bit function descriptions for Variant number and Revision numberTable 3.4
Updated Assoc field descriptionTable 3.8
Clarified cache cleaning operationExample 3.1
Updated graphicFigure 3.43
Clarified descriptions of the privilege of DMA transfers
Updated textc15, Memory remap registers
Updated performance monitor control register descriptionc15, Performance Monitor Control Register (PMNC)
Clarified graphicFigure 6.2
Added information tableTable 6.15
Updated dual TTBR descriptionFirst-level descriptor address
Added LDRD and STRD instructions
Clarified tableTable 9.2
Clarified graphicFigure 12.1
Updated C14 instruction syntaxChapter 13 Debug
Enhancement to the debug unit general descriptionAbout the debug unit
Updated Debug state descriptions
Clarified status bit[2] of TTBRs
Updated nETMWFIREADY descriptionTable A.13

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