The ARM1136JF-S processor has the following reset inputs:
The HRESETPDn is the reset signal for the PD domain.
The HRESETIRWn is the reset signal for the IRW domain.
The nRESETIN signal is the main processor reset that initializes the majority of the ARM1136JF-S logic.
The DBGnTRST signal is the DBGTAP reset. It does not reset the debug logic.
The nPORESETIN signal is the power-on reset that initializes the CP14 debug logic. See CP14 registers reset for details.
Although nPORESETIN does not reset the TAP controller, DBGTDO is held low when nPORESETIN is asserted. This means that you must deassert nPORESETIN if you want to use any JTAG functionality, including JTAG bypass.
All of these are active LOW signals that reset logic in the ARM1136JF-S processor. You must take care when designing the logic that drives these reset signals.
Inside the ARM1136JF-S processor, each reset input is synchronized to the appropriate clock signal. You do not need to synchronize the clock signals.