The reset signals present in the ARM1136JF-S processor design to enable you to reset different parts of the design independently. The reset signals, and the combinations and possible applications that you can use them in, are shown in Table 9.4.
|Reset mode||nRESETIN HRESETPDn HRESETIRWn||DBGnTRST||nPORESETIN||Application|
|Power-on reset||0||x||0||Reset at power up, full system reset. Hard reset or cold reset.|
|Processor reset||0||x||1||Reset of processor core only, watchdog reset. Soft reset or warm reset.|
|DBGTAP reset||1||0||1||Reset of DBGTAP logic, without affecting any other part of the system.|
|Normal||1||1||1||No reset. Normal run mode.|
If nRESETIN is set to 1 and nPORESETIN is set to 0 the behavior is architecturally Unpredictable. However, if nRESETIN and nPORESETIN are driven from the same source, the reset synchronization in the ARM1136JF-S processor ensures predictable behavior when the reset source is deasserted.