The PrimeCell MPMC offers:
AMBA 32-bit AHB compliancy.
Dynamic memory interface supports SDRAM, DDR-SDRAM, and low-power variants. It also supports Micron SyncFlash types of memory.
Asynchronous static memory device support including RAM, ROM, and Flash, with or without asynchronous page mode.
Specifically designed for cached processors.
Designed to work with noncritical word first, and critical word first processors, such as the ARM926EJ-S.
Read and write buffers to reduce latency and to improve performance.
Six AHB interfaces for accessing external memory.
8-bit, 16-bit, and 32-bit wide static memory support.
16-bit and 32-bit wide data bus SDRAM and SyncFlash memory support. 16-bit wide data bus DDR-SDRAM support.
Static memory features include:
asynchronous page mode read
programmable wait states
bus turnaround cycles
output enable, and write enable delays
Four chip selects for dynamic memory and four chip selects for static memory devices.
Power-saving modes dynamically control MPMCCKEOUT and MPMCCLKOUT.
Dynamic memory self-refresh mode supported by a Power Management Unit (PMU) interface or by software.
Controller supports 2K, 4K, and 8K row address dynamic memory parts. That is, typical 512Mb, 256Mb, 128Mb, 64Mb, and 16Mb parts, with 8, 16, or 32 DQ (data) bits per device.
Two reset domains enable dynamic memory contents to be preserved over a soft reset.
A separate AHB interface for programming the MPMC registers. Enables the MPMC registers to be situated in memory with other system peripheral registers.
Locked AHB transactions supported.
Support for all AHB burst types.
Little and big-endian support.
Support for the External Bus Interface (EBI) that enables the memory controller pads to be shared.
Integrated Test Interface Controller (TIC).
PrimeCell ID support.
Synchronous static memory devices (burst mode devices) are not supported.