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1.4. Product revisions

This section describes differences in functionality between product revisions of the MPMC:

r1p0-r1p1

Contains the following differences in functionality:

  • There is no change to the functionality described in this manual. See the engineering errata that accompanies the product deliverables for more information.

r1p1-r1p2

Contains the following differences in functionality:

  • Addition of the MPMCCKEINIT[3:0] signals that set the status of the SDRAM clock enable signals MPMCCKEOUT[3:0] during power-on reset. This supports the ASIC being powered down while the SDRAM is in self-refresh mode.

  • Addition of the MPMCDQMINIT signal that sets the status of the SDRAM data mask signals MPMCDQMOUT[3:0] during power-on reset. This supports the ASIC being powered down while the SDRAM is in self-refresh mode.

  • Addition of MPMCDYDDRPOL and MPMCDYDDRDLY[1:0] tie-off signals to configure power-on values of the DRP and DRD bits in the MPMCDynamicReadConfig Register.

  • Addition of MPMCDYCS5CASDLY[3] tie-off signal giving full control of the initial CAS delay value (0x0 to 0xF) for chip select 5. Previously MPMCDYCS5CASDLY[2:0] only provided control over the upper 3 bits of the CAS delay value.

  • Functionality of the E bit in the MPMCAHBControl0-5 Registers has been changed to support non-buffered writes to memory.

  • Functionality of the CS and SRMCC bits in the MPMCDynamicControl Register have been changed to support clock stopping during DDR self-refresh and therefore reducing the power consumption.

  • Addition of MPMCITIP1 Register to control the new signals and EBI signals. MPMCITIP Register renamed as MPMCITIP0 Register.

r1p2-r1p3

Contains the following differences in functionality:

  • There is no change to the functionality described in this manual. See the engineering errata that accompanies the product deliverables for more information.

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