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This glossary describes some of the terms used in this manual. Where terms can have several meanings, the meaning presented here is intended.

Application Specific Integrated Circuit (ASIC)

An integrated circuit that has been designed to perform a specific application function. It can be custom-built or mass-produced.

Application Specific Standard Part/Product (ASSP)

Another name for an Application Specific Integrated Circuit. The name implies that the device performs complete functions, and can be used as a building block in a range of products.


See Application Specific Integrated Circuit.


See Application Specific Standard Part/Product.

Coprocessor Register Transfer (CPRT)

MCR, MRC,MCRR, and MRRC instructions are Coprocessor Register Transfers.


See Coprocessor Register Transfer.

Clock gating

Gating a clock signal for a macrocell with a control signal (such as PWRDOWN) and using the modified clock that results to control the operating state of the macrocell.

Cold reset

Also known as power-on reset. Starting the processor by turning power on. Turning power off and then back on again clears main memory and many internal settings. Some program failures can lock up the processor and require a cold reset to enable the system to be used again. In other cases, only a warm reset is required.

See Also Warm reset.


A debugging system that includes a program, used to detect, locate, and correct software faults, together with custom hardware that supports software debugging.

An application that monitors and controls the operation of a second application. Usually used to find errors in the application program flow.

Embedded Trace Macrocell (ETM)

A hardware macrocell which, when connected to a processor core, outputs instruction and data trace information on a trace port.


See Embedded Trace Macrocell.


Means that the behavior is not architecturally defined, but should be defined and documented by individual implementations.

Implementation Specific

Means that the exact behavior is not architecturally defined, and need not be documented by individual implementations. This term is used when there are a number of implementation options available and the option chosen does not affect software compatibility.

Imprecise Tracing

A filtering configuration where instruction or data tracing can start or finish earlier or later than expected. Most cases cause tracing to start or finish later than expected.

For example, if TraceEnable is configured to use a counter so that tracing begins after the fourth write to a location in memory, the instruction that caused the fourth write is not traced, although subsequent instructions are. This is because the use of a counter in the TraceEnable configuration always results in Imprecise Tracing.

Jazelle architecture

The ARM Jazelle architecture extends the Thumb and ARM operating states by adding a Java state to the processor. Instruction set support for entering and exiting Java applications, real-time interrupt handling, and debug support for mixed Java/ARM applications is present. When in Java state, the processor fetches and decodes Java bytecodes and maintains the Java operand stack.

Joint Test Action Group (JTAG)

The name of the organization that developed standard IEEE 1149.1. This standard defines a boundary-scan architecture used for in-circuit testing of integrated circuit devices. It is commonly known by the initials JTAG.


See Joint Test Action Group.


A complex logic block with a defined interface and behavior. A typical VLSI system comprises several macrocells (such as an ARM9E-S, an ETM9, and a memory block) plus application-specific logic.

Power-on reset

See Cold reset.


The currently selected scan chain number in an ARM TAP controller.


An accurate transistor-level simulation tool.


See Test access port.


See Trace Capture Device.

Test Access Port (TAP)

The collection of four mandatory and one optional terminals that form the input/output and control interface to a JTAG boundary-scan architecture. The mandatory terminals are TDI, TDO, TMS, and TCK. The optional terminal is TRST.

Trace Capture Device

A generic term to describe Trace Port Analyzers, logic analyzers, and on-chip trace buffers.

Trace driver

A Remote Debug Interface target that controls a piece of trace hardware. That is, the trigger macrocell, trace macrocell, and trace capture tool.

Trace hardware

A term for a device that contains an Embedded Trace Macrocell.

Trace port

A port on a device, such as a processor or ASIC, used to output trace information.


See Trace Port Analyzer.

Trace Port Analyzer (TPA)

A hardware device that captures trace information output on a trace port. This can be a low-cost product designed specifically for trace acquisition, or a logic analyzer.


Means that the behavior of the ETM cannot be relied upon. Such conditions have not been validated. When applied to the programming of an event resource, only the output of that event resource is Unpredictable.Unpredictable behavior can affect the behavior of the entire system, because the ETM is capable of causing the core to enter debug state, and external outputs may be used for other purposes.

Warm reset

Also known as a core reset. Initializes the majority of the processor excluding the debug controller and debug logic. This type of reset is useful if you are using the debugging features of a processor.

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