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This glossary defines some of the terms used in this manual.


When the VFP9-S coprocessor detects an illegal or architecturally UNDEFINED operation, it bounces the operation to the VFP support code. The VFP support code initiates exception processing through the UNDEFINED instruction trap. The VFP9-S coprocessor bounces an instruction by asserting CPBOUNCEE in the Decode stage of a trigger instruction.

See Also Trigger instruction, Potentially exceptional instruction, and Exceptional state.

Coprocessor Data Processing (CDP)

For the VFP9-S coprocessor, CDP operations are arithmetic operations rather than load or store operations.

Default NaN mode

A mode enabled by setting the DN bit, FPSCR[25]. In this mode, all operations that result in a NaN return the default NaN, regardless of the cause of the NaN result. This mode is compliant with the IEEE 754 standard but implies that all information contained in any input NaNs to an operation is lost.

Denormalized value

See Subnormal value.

Disabled exception

An exception is disabled when its exception enable bit in the FPCSR is not set. For these exceptions, the IEEE 754 standard defines the result to be returned. An operation that generates an exception condition can bounce to the support code to produce the result defined by the IEEE 754 standard. The exception is not reported to the user trap handler.

Enabled exception

An exception is enabled when its exception enable bit in the FPCSR is set. When an enabled exception occurs, a trap to the user handler is taken. An operation that generates an exception condition might bounce to the support code to produce the result defined by the IEEE 754 standard. The exception is then reported to the user trap handler.

Exceptional state

When a potentially exceptional instruction is issued, the VFP9-S coprocessor sets the EX bit, FPEXC[31], and loads a copy of the potentially exceptional instruction in the FPINST register. If the instruction is a short vector operation, the register fields in FPINST are altered to point to the potentially exceptional iteration. When in the exceptional state, the issue of a trigger instruction to the VFP9-S coprocessor causes a bounce.

See Also Bounce, Potentially exceptional instruction, and Trigger instruction. .


The component of a floating-point number that normally signifies the integer power to which two is raised in determining the value of the represented number.


The destination register and the accumulate value in triadic operations. Sd for single-precision operations and Dd for double-precision.


The first source operand in dyadic or triadic operations. Sn for single-precision operations and Dn for double-precision.


The second source operand in dyadic or triadic operations. Sm for single-precision operations and Dm for double-precision


The floating-point field that lies to the right of the implied binary point.

Flush-to-Zero mode

A mode enabled by setting the FZ bit, FPSCR[24]. In this mode all inputs to arithmetic operations that are in the subnormal range for the input precision (-2Emin < x < 2Emin) and all results that are in the given range, before rounding, are treated as positive zero, rather than interpreted as, or converted to, a subnormal value.

IEEE 754 standard

IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE Std 754-1985. The standard that defines data types, correct operation, exception types and handling, and error bounds for floating-point systems. Most processors are built in compliance with the standard in either hardware or a combination of hardware and software.

Illegal instruction

An instruction that is architecturally UNDEFINED.


In the IEEE 754 standard format to represent infinity, the exponent is the maximum for the precision and the fraction is all zeros.

Input exception

An exception condition in which one or more of the operands for a given operation are not supported by the hardware. The operation bounces to support code for processing.

Intermediate result

An internal format used to store the result of a calculation before rounding. This format can have a larger exponent field and fraction field than the destination format.


A class of data transfer instructions that transfer 32-bit or 64-bit quantities from ARM registers to VFP9-S registers.


A class of data transfer instructions that transfer 32-bit or 64-bit quantities from VFP9-S registers to ARM registers.


Not a number. A symbolic entity encoded in a floating-point format that has the maximum exponent field and a nonzero fraction. An SNaN causes an invalid operand exception if used as an operand and a most significant fraction bit of zero. A QNaN propagates through almost every arithmetic operation without signaling exceptions and has a most significant fraction bit of one.

Potentially exceptional instruction

An instruction that is determined, based on the exponents of the operands and the sign bits, to have the potential to produce an overflow or underflow condition. Once this determination is made, the VFP enters the exceptional state and bounces the next trigger instruction issued.

See Also Bounce, Trigger instruction, and Exceptional state.

Register banks

Four banks of registers for both scalar and short vector floating-point operations. In single-precision operations, each bank contains eight single-precision registers. In double-precision operations, each bank contains four double-precision registers.


A field in a control register or instruction format is reserved if the field is to be defined by the implementation, or produces UNPREDICTABLE results if the field not cleared. These fields are reserved for use in future extensions of the architecture or are implementation-specific. All reserved bits not used by the implementation read as zero, and, when written, must be cleared.

Rounding mode

The IEEE 754 standard requires all calculations to be performed as if to an infinite precision. For example, a multiply of two single-precision values must accurately calculate the significand to twice the number of bits of the significand. To represent this value in the destination precision, rounding of the significand is often required. The IEEE 754 standard specifies four rounding modes.

In round-to-nearest mode, the result is rounded at the halfway point, with the tie case rounding up if it would clear the least significant bit of the significand, making it even. Round-toward-zero mode chops any bits to the right of the significand, always rounding down, and is used by the C, C++, and Java languages in integer conversions. Round-toward-plus-infinity mode and round-to-minus-infinity mode are used in interval arithmetic.

RunFast mode

In RunFast mode, hardware handles exceptional conditions and special operands. RunFast mode is enabled by enabling Default NaN and Flush-to-Zero modes and disabling all exceptions. In RunFast mode, the VFP9-S coprocessor does not bounce to the support code for any legal operation or any operand, but supplies a result to the destination. For all inexact and overflow results and all invalid operations that result from operations not involving NaNs, the result is as specified by the IEEE 754 standard. For operations involving NaNs, the result is the default NaN.

Scalar operation

An operation involving a single source register and a single destination register.

Short vector operation

An operation involving more than one destination register and perhaps more than one source register in the generation of the result for each destination.


The component of a binary floating-point number that consists of an explicit or implicit leading bit to the left of the implied binary point and a fraction field to the right.


The stride field, FPSCR[21:20], specifies the increment applied to register addresses in short vector operations. A stride of 00, specifying an increment of +1, causes a short vector operation to increment each vector register by +1 for each iteration, while a stride of 11 specifies an increment of +2.

Subnormal value

A representation of a value in the range (-2Emin < x < 2Emin). In the IEEE 754 standard format for single-precision and double-precision operands, a subnormal value has a zero exponent and a leading significant bit of zero. The IEEE 754 standard requires that the generation and manipulation of subnormal operands be performed with the same precision as normal operands.

Support code

Software that must be used to complement the hardware to provide compatibility with the IEEE 754 standard. The support code must have a library of routines that performs supported functions, such as divide with unsupported inputs or inputs that might generate an exception as well as operations beyond the scope of the hardware. The support code must also have a set of exception handlers to process exceptional conditions in compliance with the IEEE 754 standard.

The support code is required to perform implemented functions to emulate proper handling of any unsupported data type or data representation. The routines can be written to use the VFP9-S coprocessor in their intermediate calculations if care is taken to restore the user state at the exit of the routine.


An exceptional condition that has the respective exception enable bit set in the FPSCR register. The user provided trap handler is executed.

Trigger instruction

The instruction that causes a bounce at the time it is issued. A potentially exceptional instruction causes the VFP9-S coprocessor to enter the exceptional state. The next instruction, unless it is an FMXR or FMRX instruction accessing the FPEXC, FPINST, or FPSID register, causes a bounce, beginning exception processing. The trigger instruction is not necessarily exceptional, and no processing of it is performed. It is retried at the return from exception processing of the potentially exceptional instruction.

See Also Bounce, Potentially exceptional instruction, and Exceptional state.


Indicates an instruction that generates an UNDEFINED instruction trap. See the ARM Architecture Reference Manual for more information on ARM exceptions.


The result of an instruction or control register field value that cannot be relied upon. UNPREDICTABLE instructions or results must not represent security holes, or halt or hang the processor, or any parts of the system.

Unsupported values

Specific data values that are not processed by the hardware but bounced to the support code for completion. These data can include infinities, NaNs, subnormal values, and zeros. An implementation is free to select which of these values is supported in hardware fully or partially, or requires assistance from support code to complete the operation. Any exception resulting from processing unsupported data is trapped to user code if the corresponding exception enable bit for the exception is set.

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