This glossary describes some of the terms used in this manual. Where terms can have several meanings, the meaning presented here is intended.
- Advanced microcontroller bus architecture
The ARM open standard for on-chip buses. AHB is specified in this standard.
See Advanced microcontroller bus architecture.
An eight-bit data item.
- Clock gating
Gating a clock signal for a macrocell with a control signal, and using the modified clock that results to control the operating state of the macrocell.
A debugging system which includes a program, used to detect, locate, and correct software faults, together with custom hardware that supports software debugging.
- Embedded trace macrocell
A hardware macrocell which, when connected to a processor core, outputs instruction and data trace information on a trace port.
See Embedded trace macrocell.
A 16-bit data item.
See Joint test action group.
- Joint test action group
The name of the organization that developed standard IEEE 1149.1. This standard defines a boundary-scan architecture used for in-circuit testing of integrated circuit devices. It is commonly known by the initials JTAG.
A complex logic block with a defined interface and behavior. A typical VLSI system comprises several macrocells (such as an ETM9 and a memory block) plus application-specific logic.
A field in a control register or instruction format is reserved if the field is to be defined by the implementation, or produces UNPREDICTABLE results if the contents of the field are set as specified. These fields are reserved for use in future extensions of the architecture or are implementation-specific. All reserved bits not used by the implementation must be written as zero and will be read as zero.
See Test access port.
- Test access port
The collection of four mandatory and one optional terminals that form the input and output and control interface to a JTAG boundary-scan architecture. The mandatory terminals are TDI, TDO, TMS, and TCK. The optional terminal is nTRST.
See Trace port analyzer.
- Trace driver
A target that controls a piece of trace hardware. That is, the trigger macrocell, trace macrocell and trace capture tool.
- Trace hardware
A term for a device that contains an ETM.
- Trace port analyzer
The trace port analyzer is an external hardware device that stores the information from the trace port, for example a logic analyzer or a low-cost collection unit. The debug tools retrieve data from the analyzer, reconstruct an historical view of the processor's activity including data accesses, as well as configuring the macrocell using the JTAG port. Powerful user-definable filters allow you to limit the amount of information captured in search of a bug, reducing upload time from the trace port analyzer.
For reads, the data returned when reading from this location is unpredictable. It can have any value. For writes, writing to this location causes unpredictable behavior, or an unpredictable change in device configuration. UNPREDICTABLE instructions must not halt or hang the processor, or any part of the system.
A 32-bit data item.