This glossary describes some of the terms used in this manual. Where terms can have several meanings, the meaning presented here is intended.
- Advanced Microcontroller Bus Architecture (AMBA)
AMBA is the ARM open standard for multi-master on-chip buses, capable of running with multiple masters and slaves. It is an on-chip bus specification that details a strategy for the interconnection and management of functional blocks that make up a System-on-Chip (SoC). It aids in the development of embedded processors with one or more CPUs or signal processors and multiple peripherals. AMBA complements a reusable design methodology by defining a common backbone for SoC modules. AHB conforms to this standard.
See Also Advanced High-performance Bus and AHB-Lite.
See Advanced High-performance Bus.
AHB-Lite is a subset of the full AHB specification. It is intended for use in designs where only a single AHB master is used. This can be a simple single AHB master system or a multi-layer AHB system where there is only one AHB master on a layer.
See Advanced Microcontroller Bus Architecture.
See Advanced Peripheral Bus.
An eight-bit data item.
- Clock gating
Gating a clock signal for a macrocell with a control signal, and using the modified clock that results to control the operating state of the macrocell.
- Data Abort
An indication from a memory system to a core that it must halt execution of an attempted illegal memory access. A Data Abort is attempting to access invalid data memory.
A debugging system that includes a program, used to detect, locate, and correct software faults, together with custom hardware that supports software debugging.
An application that monitors and controls the operation of a second application. Usually used to find errors in the application program flow
- Embedded Trace Macrocell (ETM)
A hardware macrocell which, when connected to a processor core, outputs instruction and data trace information on a trace port.
See Embedded Trace Macrocell.
A 16-bit data item.
See Joint Test Action Group.
- Joint Test Action Group (JTAG)
The name of the organization that developed standard IEEE 1149.1. This standard defines a boundary-scan architecture used for in-circuit testing of integrated circuit devices. It is commonly known by the initials JTAG.
A complex logic block with a defined interface and behavior. A typical VLSI system comprises several macrocells (such as an ETM9 and a memory block) plus application-specific logic.
A field in a control register or instruction format is reserved if the field is to be defined by the implementation, or produces Unpredictable results if the contents of the field are set as specified. These fields are reserved for use in future extensions of the architecture or are implementation-specific. All reserved bits not used by the implementation must be written as zero and will be read as zero.
See Test Access Port.
- Test Access Port (TAP)
The collection of four mandatory and one optional terminals that form the input and output and control interface to a JTAG boundary-scan architecture. The mandatory terminals are DBGTDI, DBGTDO, DBGTMS, and DBGTCK. The optional terminal is nDBGTRST.
See Trace Port Analyzer.
- Trace driver
A target that controls a piece of trace hardware. That is, the trigger macrocell, trace macrocell and trace capture tool.
- Trace hardware
A term for a device that contains an ETM.
- Trace port analyzer (TPA)
The trace port analyzer is an external hardware device that stores the information from the trace port, for example a logic analyzer or a low-cost collection unit. The debug tools retrieve data from the analyzer, reconstruct an historical view of the processor's activity including data accesses, as well as configuring the macrocell using the JTAG port. Powerful user-definable filters enable you to limit the amount of information captured in search of a bug, reducing upload time from the trace port analyzer.
For reads, the data returned when reading from this location is unpredictable. It can have any value. For writes, writing to this location causes unpredictable behavior, or an unpredictable change in device configuration. Unpredictable instructions must not halt or hang the processor, or any part of the system.
A 32-bit data item. Words are normally word-aligned in ARM systems.