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Appendix C. Revisions

This appendix describes the technical changes between released issues of this book.

Table C.1. Differences between issue G and issue H
Change description of Main ID Register.Table 3.4All revisions
Correct description of Control Register bit functionsTable 3.39All revisions
Expanded Note to include description of Monitor mode access to non-secure banked copies of registers.c1, Secure Configuration RegisterAll revisions
Improve description of MVA alignment for L1 operations.Table 3.69All revisions
Improve description of DMA user access bitsTable 3.107All revisions
Correct B and C bit descriptions for the TLB Lockdown Attributes RegisterTable 3.152All revisions
Correct user permissions for memory regions.Table 6.1All revisions
Improve description of page table attribute restrictions.Restriction on page table attributesAll revisions
Improve description of INTSYNCEN signal.

Table 12.1

Synchronization of the VIC port signals

Table A.4

All revisions
Improve description of DBGEN signal.

Table 13.22

External signals

All revisions
Correct instruction for entering debug stateEntering Debug stateAll revisions
Deselect DTR in debug sequence.Writing memory as wordsAll revisions
Correct description of nETMWFIREADY signal.Table A.13All revisions