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A.1. ETM9CSSingle Signals

Table A.1 lists the ETM9CSSingle signals in alphabetical order. Clock domains, where specified, give the clock on which input signals must be generated and output signals sampled. See the CoreSight ETM9 Integration Manual for information about signals and connectivity.

ETM9CSSingle signals
Signal nameInput/OutputDescriptionClock domains
ASICCTL[7:0]OutputContents of the ASIC control register.CLK
ATCLKInputATB interface clock.-
ATCLKENInputEnable signal for ATCLK. ATCLK
ATRESETnInputInternal trace bus reset. Resets all registers in the ATCLK domain. Active LOW.Internally synchronized
BIGENDInputWhen HIGH indicates that the processor is operating in big-endian mode.CLK
CHSD[1:0]Input Coprocessor handshake decode signals. CLK
CHSE[1:0]InputCoprocessor handshake execute signals. CLK
CLKInputThis is the main clock for the ETM9CSSingle, and must be the same as the processor clock.-
CLKENInputIndicates when the ARM9 processor stalls waiting for memory accesses to complete. This signal is connected to an output from the ARM9 processor. CLK
CORESELECT[2:0]OutputWhere an ETM is shared between multiple cores, this signal specifies which core to trace.-
DA[31:0]InputData address.CLK
DABORTInputThis signal indicates that the data transfer requested by the processor has been aborted.CLK
DBGACKInputIndicates that the core is in debug state. This is connected to the core general purpose DBGACK output, so that it can be used to determine when ETMDBGRQ can be deasserted. It is also used for other purposes in the ETM, and care must be taken to ensure the timing of this signal is appropriate because it does not come through the main core/ETM interface.CLK
DBGENInputWhen HIGH indicates that invasive debug is enabled.-
DD[31:0]Input Write data value.CLK
DDIN[31:0]Input Read data value.CLK
DMAS[1:0]Input Data memory access size.CLK
DnMREQInputIf this signal is LOW at the end of a cycle then the processor requires a data memory access in the following cycle.CLK
DnRWInput If this signal is LOW at the end of a cycle then any data memory access in the following cycle is a read. If this signal is HIGH then it is a write.CLK
DSEQInputIf this signal is HIGH at the end of the cycle then any data memory access in the following cycle is sequential from the last data memory access.CLK
ETBTRACEDATA[31:0]OutputProvides trace data for ETB capture.ATCLK
ETBTRACEVALIDOutputIndicates that trace data is valid.ATCLK
ETBTRIGGEROutputIndicates trigger condition.ATCLK
ETMDBGRQOutputRequest from the CoreSight ETM9 for the core to enter debug state. This must be ORed with any ASIC-level DBGRQ signals before being connected to the core EDBGRQ input.CLK
ETMENOutputWhen HIGH, ETMTRACEPORT is enabled. When LOW, logic related to the to the ETMTRACEPORT can be clock-gated.CLK
ETMPWRUPOutput

When HIGH, indicates that CoreSight ETM9 is in use.

When LOW:

  • external logic supporting CoreSight ETM9 can be clock-gated to conservepower.

  • the ARM9 processor disables the CoreSight ETM9 interface

  • logic within CoreSight ETM9 is clock-gated to conserve power.

CLK
EXTIN[3:0]InputExternal input resources.See footnote [1]
EXTINACK[3:0]Output

Acknowledge signal for the EXTIN[3:0] bus. When EXTSBYPASS is HIGH, EXTINACK[3:0] are not valid and can be ignored.

-
EXTOUT[1:0]OutputExternal outputs.See footnote a
EXTOUTACK[1:0]Input

Acknowledge signals for the EXTOUT[1:0] bus. When EXTSBYPASS is HIGH, these signals must be tied LOW.

-
EXTSBYPASSInput

EXTSBYPASS is a single bit input to the ETM that is used to bypass the synchronization of the external inputs EXTIN[3:0] and external outputs EXTOUT[1:0].

When EXTSBYPASS is LOW:

  • a HIGH output on any bit of EXTOUT[1:0] is held until the corresponding bit of EXTOUTACK[1:0] is asserted HIGH.

  • a HIGH on any bit of EXTIN[3:0] must remain held until the ETM asserts the corresponding bit of EXTINACK[3:0] HIGH.

When EXTSBYPASS is HIGH, EXTOUT[1:0] outputs are valid on the rising edge of CLK and EXTIN[3:0] inputs must be valid on the rising edge of CLK.

-
FIFOPEEK[8:0]OutputFor validation purposes only. Indicates when various events occur before being written to the FIFO.CLK
HIVECSInputWhen this signal is LOW the exception vectors start at address 0x0000 0000. When HIGH the exception vectors start at address 0xFFFF 0000. CLK
IA[31:0]Input Instruction address.CLK
ID15To11[15:11]Input Instruction data field.CLK
ID31To25[31:25]Input Instruction data field.CLK
IJBITInputWhen this signal is HIGH it indicates the ARM processor is in JAVA state. This signal is valid with the address.CLK
JTAGSBYPASSInputJTAGSBYPASS is a single bit input to the ETM that is used to bypass the JTAG synchronization.-
InMREQInputIf this signal is LOW at the end of the cycle then the processor requires an instruction memory access in the following cycle.CLK
INSTREXECInputThis signal indicates the instruction in the Execute stage of the pipeline follower of the ETM has been executed.CLK
INSTRVALIDInputThis signal indicates the instruction in the Execute stage is valid and has not been flushed.CLK
ISEQInputIf this signal is HIGH at the end of the cycle then any instruction memory access in the following cycle is sequential from the last instruction memory access.CLK
ITBITInputWhen HIGH this signal indicates the ARM processor is in Thumb state. When this signal is LOW the processor is in ARM state. This signal is valid with the address.CLK
LATECANCELInputCancel coprocessor instruction. If this signal is HIGH during the first memory cycle of a coprocessor instruction, then the coprocessor must cancel the instruction without changing any internal state. This signal is only asserted in cycles where the previous instruction accessed memory and a Data Abort occurred.CLK
MAXCORES[2:0]InputWhere a CoreSight ETM9 is shared between multiple cores, this signal specifies the number of cores the ETM can trace. It must be tied to the number of cores sharing the ETM minus 1.-
MAXEXTIN[2:0]InputExternal inputs supported by the ASIC (maximum 4). This appears in the configuration code register.-
MAXEXTOUT[1:0]InputExternal outputs supported by the ASIC (maximum 2). This appears in the configuration code register.-
MAXPORTSIZE[3:0]InputMaximum port size supported. See MAXPORTSIZE in ETM9CS and ETM9CSSingle.-
NIDENInputNon-invasive debug enable.Internally synchronized
nPORESETInputMain power on reset. Resets all registers in the CLK domain.Internally synchronized
nTRSTInputJTAG interface reset. Active LOW.-
PADDR[11:2]InputSystem APB Address Bus.PCLK
PASSInputThis signal indicates that the coprocessor instruction in the Execute stage of the pipeline follower of the ETM has been executed.CLK
PCLKInputSystem APB interface clock-
PCLKENInputSystem APB clock enable.PCLK
PENABLEInputThe system APB interface is enabled for a transfer.PCLK
PORTMODE[2:0]OutputCurrently requested port mode.CLK
PORTSIZE[3:0]OutputCurrently requested port size.CLK
PRDATA[31:0]OutputSystem APB read data.PCLK
PREADYOutputUsed to extend transfers, and to arbitrate between JTAG and APB accesses.PCLK
PRESETnInputSystem APB interface reset. Active LOW.Internally synchronized
PROCID[31:0]InputProcess ID.CLK
PROCIDWRInputThis signal must be asserted whenever the PROCID bus changes. This causes the ETM to output the new context ID at the next available opportunity.CLK
PSELInputSystem APB select signal.PCLK
PSLVERROutputSystem APB error signal PCLK
PWDATA[31:0]InputSystem APB write data.PCLK
PWRITEInputSystem APB transfer direction (!Read/Write).PCLK
RANGEOUT0 InputThis signal indicates that the corresponding watchpoint unit has matched the conditions currently present on the address, control and data buses. This signal is independent of the state of the enable control bit of the watchpoint unit.CLK
RANGEOUT1 InputThis signal indicates that the corresponding watchpoint unit has matched the conditions currently present on the address, control and data buses. This signal is independent of the state of the enable control bit of the watchpoint unit.CLK
RSTBYPASSInputReset synchronization bypass.-
RTCKOutputJTAG interface return clock-
SEInputScan enable.-
TCKInputJTAG interface clock .-
TDIInputTest data in. Must be connected to TDI input to the core.See footnote b
TDOOutputTest data out. Must be multiplexed externally with TDO from the core, controlled by TDOSEL.PCLK
TDOSELOutputSelects between core and ETM TDO.PCLK
TMSInputTest mode select. Must be connected to the TMS input to the core.See footnote [2]
TRACECLKOutputExported clock for TRACEDATA[31:0] and TRACECTL. Data is valid on both edges of this clock for maximum integrity.-
TRACECTLOutputUsed by trace capture devices. This signal is valid for the same time as TRACEDATA.Trigger = TRACECTL & !TRACEDATA[0] TraceDisabled = TRACECTL & TRACEDATA[0].TRACECLK
TRACEDATA[31:0]Output32-bit trace port. Only data on this bus must be captured.TRACECLK
ZIFIRSTInputWhen the ARM9 processor is in Java state this signal is asserted on the first ARM instruction to be traced. (No more than two instructions are ever traced for a bytecode.) If only one ARM instruction is traced in Java state, both ZIFIRST and ZILAST are asserted.CLK
ZILASTInputWhen the ARM9 processor is in Java state this signal is asserted on the last ARM instruction to be traced. (No more than two instructions are ever traced for a bytecode.) If only one ARM instruction is traced in Java state, both ZIFIRST and ZILAST are assertedCLK

[1] If EXTSBYPASS is 1, then EXTIN[3:0] must be generated on CLK and EXTOUT[1:0] must be sampled on CLK. If EXTSBYPASS is 0, then there is no such restriction. See CoreSight ETM9 Integration Manual for more details.

[2] If JTAGSBYPASS is 1, then the JTAG interface inputs must be synchronous to PCLK. If JTAGSBYPASS is 0, then the JTAG inputs are synchronized internally.

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