Table A.2 ETM9CS signals in alphabetical order. Clock domains, where specified, give the clock on which input signals must be generated and output signals sampled. See the CoreSight ETM9 Integration Manual for information about signals and connectivity.
|Signal name||Input/output||Description||Clock domains|
|AFREADYM||Output||ATB interface FIFO flush finished.||ATCLK|
|AFVALIDM||Input||ATB interface FIFO flush request.||ATCLK|
|ASICCTL[7:0]||Output||Contents of the ASIC control register.||CLK|
|ATBYTESM[1:0]||Output||Size of ATDATAM.||ATCLK|
|ATCLK||Input||ATB interface clock.||-|
|ATCLKEN||Input||Enable signal for ATCLK.||ATCLK|
|ATDATAM[31:0]||Output||ATB interface data.||ATCLK|
|ATIDM[6:0]||Output||ATB interface trace source ID.||ATCLK|
|ATREADYM||Input||ATDATA can be accepted.||ATCLK|
|ATRESETn||Input||ATB interface reset.||Internally synchronized|
|ATVALIDM||Output||ATB interface data valid.||ATCLK|
|BIGEND||Input||When HIGH indicates that the processor is operating in big-endian mode.||CLK|
|CHSD[1:0]||Input||Coprocessor handshake decode signals.||CLK|
|CHSE[1:0]||Input||Coprocessor handshake execute signals.||CLK|
|CLK||Input||This is the main clock for the ETM9CS, and must be the same as the processor clock.||-|
|CLKEN||Input||Indicates when the ARM9 processor stalls waiting for memory accesses to complete. This signal is connected to an output from the ARM9 processor.||CLK|
|CORESELECT[2:0]||Output||Where an ETM is shared between multiple cores, this signal specifies which core to trace.||-|
|DABORT||Input||This signal indicates that the data transfer requested by the processor has been aborted.||CLK|
|DBGACK||Input||Indicates that the core is in debug state. This is connected to the core general purpose DBGACK output, so that it can be used to determine when ETMDBGRQ can be deasserted. It is also used for other purposes in the ETM, and care must be taken to ensure the timing of this signal is appropriate because it does not come through the main core/ETM interface.||CLK|
|DBGEN||Input||When HIGH indicates that invasive debug is enabled.||-|
|DD[31:0]||Input||Write data value||CLK|
|DDIN[31:0]||Input||Read data value.||CLK|
|DMAS[1:0]||Input||Data memory access size.||CLK|
|DnMREQ||Input||If this signal is LOW at the end of a cycle then the processor requires a data memory access in the following cycle.||CLK|
|DnRW||Input||If this signal is LOW at the end of a cycle then any data memory access in the following cycle is a read. If this signal is HIGH then it is a write.||CLK|
|DSEQ||Input||If this signal is HIGH at the end of the cycle then any data memory access in the following cycle is sequential from the last data memory access.||CLK|
|ETMDBGRQ||Output||Request from the CoreSight ETM9 for the core to enter debug state. This must be ORed with any ASIC-level DBGRQ signals before being connected to the core EDBGRQ input.||CLK|
|ETMEN||Output||When HIGH, the ATB interface is enabled. When LOW, logic related to the to the ATB interface can be clock-gated.||CLK|
When HIGH, indicates that CoreSight ETM9 is in use.
|ETPSUP||Input||Indicates a trace port is connected.||-|
|EXTIN[3:0]||Input||External input resources.||See footnote |
Acknowledge signal for the EXTIN[3:0] bus. When EXTSBYPASS is HIGH, EXTINACK[3:0] are not valid and can be ignored.
|EXTOUT[1:0]||Output||External outputs.||See footnote a|
Acknowledge signals for the EXTOUT[1:0] bus. When EXTSBYPASS is HIGH, these signals must be tied LOW.
EXTSBYPASS is a single bit input to the ETM that is used to bypass the synchronization of the external inputs EXTIN[3:0] and external outputs EXTOUT[1:0].
When EXTSBYPASS is LOW:
When EXTSBYPASS is HIGH, EXTOUT[1:0] outputs are valid on the rising edge of CLK and EXTIN[3:0] inputs must be valid on the rising edge of CLK.
|FIFOPEEK[8:0]||Output||For validation purposes only. Indicates when various events occur before being written to the FIFO.||CLK|
|HIVECS||Input||When this signal is LOW the exception vectors
start at address ||CLK|
|ID15To11[15:11]||Input||Instruction data field.||CLK|
|ID31To25[31:25]||Input||Instruction data field.||CLK|
|IJBIT||Input||When this signal is HIGH it indicates the ARM processor is in JAVA state. This signal is valid with the address.||CLK|
|InMREQ||Input||If this signal is LOW at the end of the cycle then the processor requires an instruction memory access in the following cycle.||CLK|
|INSTREXEC||Input||This signal indicates the instruction in the Execute stage of the pipeline follower of the ETM has been executed.||CLK|
|INSTRVALID||Input||This signal indicates the instruction in the Execute stage is valid and has not been flushed.||CLK|
|ISEQ||Input||If this signal is HIGH at the end of the cycle then any instruction memory access in the following cycle is sequential from the last instruction memory access.||CLK|
|ITBIT||Input||When HIGH this signal indicates the ARM processor is in Thumb state. When this signal is LOW the processor is in ARM state. This signal is valid with the address.||CLK|
|LATECANCEL||Input||Cancel coprocessor instruction. If this signal is HIGH during the first memory cycle of a coprocessor instruction, then the coprocessor must cancel the instruction without changing any internal state. This signal is only asserted in cycles where the previous instruction accessed memory and a Data Abort occurred.||CLK|
|MAXCORES[2:0]||Input||Where an ETM is shared between multiple cores, this signal specifies the number of cores the ETM can trace. It must be tied to the number of cores sharing the ETM minus 1.||-|
|MAXEXTIN[2:0]||Input||External inputs supported by the ASIC (maximum 4). This appears in the configuration code register.||-|
|MAXEXTOUT[1:0]||Input||External outputs supported by the ASIC (maximum 2). This appears in the configuration code register.||-|
|MAXPORTSIZE[3:0]||Input||Maximum port size supported. See MAXPORTSIZE in ETM9CS and ETM9CSSingle.||-|
|NIDEN||Input||Non-invasive debug enable.||-|
|nPORESET||Input||Main reset. Resets all registers in the CLK domain.||Internally synchronized|
|PADDRDBG[11:2]||Input||Debug APB Address Bus.||PCLKDBG|
Originates as an output signal from either the ETMJTAGPORT or Debug Access Port (DAP).
PADDRDBG31 at logic 1 indicates an access from hardware (JTAG).
PADDRDBG31 at logic 0 indicates an access from software.
|PASS||Input||This signal indicates that the coprocessor instruction in the Execute stage of the pipeline follower of the ETM has been executed.||CLK|
|PCLKDBG||Input||Debug APB clock.||-|
|PCLKENDBG||Input||Debug APB clock enable.||PCLKDBG|
|PENABLEDBG||Input||The Debug APB interface is enabled for a transfer.||PCLKDBG|
|PORTMODE[2:0]||Output||Currently requested port mode. Not used in a CoreSight system.||CLK|
|PORTSIZE[3:0]||Output||Currently requested port size. Not used in a CoreSight system||CLK|
|PRDATADBG[31:0]||Output||Debug APB read data.||PCLKDBG|
|PREADYDBG||Output||Used to extend Debug APB transfers.||PCLKDBG|
|PRESETDBGn||Input||Debug APB interface reset.||Internally synchronized|
|PROCIDWR||Input||This signal must be asserted whenever the PROCID bus changes. This causes the ETM to output the new context ID at the next available opportunity.||CLK|
|PSELDBG||Input||Debug APB Slave select signal.||PCLKDBG|
|PSLVERRDBG||Output||Debug APB error signal||PCLKDBG|
|PWDATADBG[31:0]||Input||Debug APB write data.||PCLKDBG|
|PWRITEDBG||Input||Debug APB transfer direction (!Read/Write).||PCLKDBG|
|RANGEOUT0||Input||This signal indicates that the corresponding watchpoint unit has matched the conditions currently present on the address, control and data buses. This signal is independent of the state of the enable control bit of the watchpoint unit.||CLK|
|RANGEOUT1||Input||This signal indicates that the corresponding watchpoint unit has matched the conditions currently present on the address, control and data buses. This signal is independent of the state of the enable control bit of the watchpoint unit.||CLK|
|RSTBYPASS||Input||Reset synchronization bypass.||-|
|TRIGOUT||Output||Trigger request status signal.||See footnote |
|TRIGOUTACK||Input||ATB trigger acknowledge.||-|
|TRIGSBYPASS||Input||Trigger synchronization bypass.||-|
|ZIFIRST||Input||When the ARM9 processor is in Java state this signal is asserted on the first ARM instruction to be traced. (No more than two instructions are ever traced for a bytecode.) If only one ARM instruction is traced in Java state, both ZIFIRST and ZILAST are asserted.||CLK|
|ZILAST||Input||When the ARM9 processor is in Java state this signal is asserted on the last ARM instruction to be traced. (No more than two instructions are ever traced for a bytecode.) If only one ARM instruction is traced in Java state, both ZIFIRST and ZILAST are asserted||CLK|
 If EXTSBYPASS is 1, then EXTIN[3:0] must be generated on CLK and EXTOUT[1:0] must be sampled on CLK. If EXTSBYPASS is 0, then there is no such restriction. See CoreSight ETM9 Integration Manual for further details.
 If TRIGSBYPASS is 1, then TRIGOUT must be sampled on ATCLK. If TRIGSBYPASS is 0, then there is no such restriction.