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B.1. ETM9CSSingle I/O timing parameters

Signals are classified according to the percentage of the clock period taken up by internal logic.

  • For inputs this is the delay between the input port and the first register.

  • For outputs this is the delay between the last register and the output port.

The timing classifications used are:

Early

Less than 20% of the period described above.

Middle

Between 20% and 80% of the period described above.

Late

Greater than 80% of the period described above.

Table B.1 describes the ETM9CSSingle signal timing parameters.

ETM9CSSingle signal timing parameters
Signal nameTiming classificationInput/ Output
ASICCTL[7:0] Middle Output
ATCLK-Input
ATCLKEN LateInput
ATRESETnLateInput
BIGENDMiddleInput
CHSD[1:0]MiddleInput
CHSE[1:0]MiddleInput
CLK-Input
CORESELECT[2:0] Middle Output
CLKENMiddleInput
DA[31:0]MiddleInput
DABORTMiddleInput
DBGACK Middle Input
DBGENLateInput
DD[31:0]Middle Input
DDIN[31:0]MiddleInput
DMAS[1:0]MiddleInput
DnMREQMiddleInput
DnRWMiddleInput
DSEQMiddleInput
ETBTRACEDATA[31:0]MiddleOutput
ETBTRACEVALIDMiddleOutput
ETBTRIGGER Middle Output
ETMDBGRQ Middle Output
ETMEN Middle Output
ETMPWRUPLateOutput
EXTIN[3:0] Middle Input
EXTINACK[3:0] MiddleOutput
EXTOUT[1:0] Middle Output
EXTOUTACK[1:0] MiddleInput
EXTSBYPASSMiddle Input
FIFOPEEK[8:0] Middle Output
HIVECSMiddleInput
IA[31:0]MiddleInput
ID15To11[15:11]MiddleInput
ID31To25[31:25]MiddleInput
IJBITMiddleInput
JTAGSBYPASSLateInput
InMREQMiddleInput
INSTREXECMiddleInput
INSTRVALIDMiddleInput
ISEQMiddleInput
ITBITMiddleInput
LATECANCELMiddleInput
MAXCORES[2:0] Middle Input
MAXEXTIN[2:0] Middle Input
MAXEXTOUT[1:0] Middle Input
MAXPORTSIZE[3:0] Middle Input
NIDEN Late Input
nPORESET Late Input
nTRST Middle Input
PADDR[11:2] Late Input
PASSMiddleInput
PCLK-Input
PCLKEN Late Input
PENABLE Late Input
PORTMODE[2:0] Middle Output
PORTSIZE[3:0] Middle Output
PRDATA[31:0] Late Output
PREADY Late Output
PRESETnMiddleInput
PROCID[31:0]MiddleInput
PROCIDWRMiddleInput
PSEL Late Input
PSLVERRLateOutput
PWDATA[31:0] Late Input
PWRITE Late Input
RANGEOUT0 MiddleInput
RANGEOUT1 MiddleInput
RSTBYPASS Late Input
RTCKMiddleOutput
SELate Input
TCKLateInput
TDILateInput
TDO MiddleOutput
TDOSEL Middle Output
TMSLateInput
TRACECLK Middle Output
TRACECTL Middle Output
TRACEDATA[31:0] Middle Output
ZIFIRSTMiddleInput
ZILASTMiddleInput

Note

Actual clock frequencies and input and output timing constraints vary according to application requirements and the silicon process technologies used. The maximum operating clock frequencies change according to the constraints and the process technology you use.

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