You copied the Doc URL to your clipboard.

B.2. ETM9CS I/O timing parameters

Signals are classified according to the percentage of the clock period taken up by internal logic.

  • For inputs this is the delay between the input port and the first register.

  • For outputs this is the delay between the last register and the output port.

The timing classifications used are:

Early

Less than 20% of the period described above.

Middle

Between 20% and 80% of the period described above.

Late

Greater than 80% of the period described above.

Table B.2 describes the ETM9CS signal timing parameters.

ETM9CS signal timing parameters
Signal nameTiming classificationInput/ Output
AFREADYMMiddle Output
AFVALIDMMiddleInput
ASICCTL[7:0] Middle Output
ATBYTESM[1:0]MiddleOutput
ATCLK-Input
ATCLKEN MiddleInput
ATDATAM[31:0]Middle Output
ATIDM[6:0]MiddleInput
ATREADYMMiddleInput
ATRESETnLateInput
ATVALIDMMiddleOutput
BIGENDMiddleInput
CHSD[1:0]MiddleInput
CHSE[1:0]MiddleInput
CLK-Input
CLKEN Middle Input
CORESELECT[2:0] Middle Output
DA[31:0] Middle Input
DABORTMiddleInput
DBGACK MiddleInput
DBGENLateInput
DD[31:0]MiddleInput
DDIN[31:0]MiddleInput
DMAS[1:0]MiddleInput
DnMREQMiddleInput
DnRWMiddleInput
DSEQMiddleInput
ETMDBGRQ Middle Output
ETMEN Middle Output
ETMPWRUPLateOutput
ETPSUPLateInput
EXTIN[3:0] Middle Input
EXTINACK[3:0]MiddleOutput
EXTOUT[1:0] Middle Output
EXTOUTACK[1:0]MiddleInput
EXTSBYPASSMiddleInput
FIFOPEEK[8:0] Middle Output
HIVECSMiddleInput
IA[31:0]MiddleInput
ID15To11[15:11]MiddleInput
ID31To25[31:25]Middle Input
IJBITMiddle Input
InMREQMiddle Input
INSTREXECMiddle Input
INSTRVALIDMiddleInput
ISEQ MiddleInput
ITBIT MiddleInput
LATECANCEL Middle Input
MAXCORES[2:0] Middle Input
MAXEXTIN[2:0] Middle Input
MAXEXTOUT[1:0] Middle Input
MAXPORTSIZE[3:0] Middle Input
NIDEN Late Input
nPORESET Late Input
PADDRDBG[11:2] Middle Input
PADDRDBG31MiddleInput
PASSMiddleInput
PCLKDBG-Input
PCLKENDBGMiddleInput
PENABLEDBG Middle Input
PORTMODE[2:0] Middle Output
PORTSIZE[3:0] MiddleOutput
PRDATADBG[31:0] MiddleOutput
PREADYDBG Middle Output
PRESETDBGnLate Input
PROCID[31:0]Middle Input
PROCIDWRMiddleInput
PSELDBG MiddleInput
PSLVERRDBG MiddleOutput
PWDATADBG[31:0] Middle Input
PWRITEDBG Middle Input
RANGEOUT0 MiddleInput
RANGEOUT1 MiddleInput
RSTBYPASS Late Input
SE Late Input
TRIGOUT Middle Output
TRIGOUTACK Middle Input
TRIGSBYPASS Middle Input
ZIFIRST Middle Input
ZILAST Middle Input

Note

Actual clock frequencies and input and output timing constraints vary according to application requirements and the silicon process technologies used. The maximum operating clock frequencies change according to the constraints and the process technology you use.

Was this page helpful? Yes No