You copied the Doc URL to your clipboard.


ETMTRACEPORT takes the ETM trace output stream and converts it to a form suitable for taking off-chip. It also creates and exports a clock, TRACECLK, used by the off-chip capture device to sample the converted trace data.

TRACECLK and its associated data are generated from ATCLK. CoreSight ETM9CSSingle supports asynchronous CLK, PCLK, and ATCLK clock domains. Therefore, it is not necessary for the trace port clock frequency to be an integer division of the main clock.

ETMTRACEPORT sets its trace port configuration according to the values of PORTSIZE[3:0] output from CoreSight ETM9. ETMTRACEPORT only supports trace port sizes of 2, 4, 8, 16 and 32 bits, because ETMTRACEPORT only receives 32-bit data packets from the ETM, and all these port sizes wholly divide into 32.

See CoreSight ETM9 Configuration and Sign-off Guide for implementation details about delaying TRACECLK.

Was this page helpful? Yes No