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A.2. ETM11CS Signals

Table A.2 lists the ETM11CS signals in alphabetical order. Clock domains, where specified, give the clock on which input signals must be generated and output signals sampled. See the CoreSight ETM11 Integration Manual for information about signals and connectivity.

ETM11CS signals
SignalInput/ outputDescriptionDomains
AFREADYMOutputATB interface FIFO flush finished.ATCLKVSOC
AFVALIDMInputATB interface FIFO flush request.ATCLKVSOC
ASICCTL[7:0]OutputContents of the ASIC control register.CLKVCORE
ATCLKInputATB interface clock.-VSOC
ATCLKENInputEnable signal for ATCLK. ATCLKVSOC
ATDATAM[31:0]OutputATB interface data.ATCLKVSOC
ATIDM[6:0]OutputATB interface trace source ID.ATCLKVSOC
ATRESETnInputATB interface reset.Internally synchronizedVSOC
ATVALIDMOutput ATB interface data valid.ATCLKVSOC
CFGBIGENDInputOutput signal from ARM11 family cores. CFGBIGEND at logic 1 indicates that the core is operating in big-endian (BE-32) mode.CLKVSOC
CLKInputThis is the main clock for the ETM11CS.-VSOC
CORESELECT[2:0]OutputWhere an ETM is shared between multiple cores, this signal specifies which core to trace.-VCORE

Indicates that the core is in debug state.

This signal is connected to the core general purpose DBGACK output, so that it can be used to determine when ETMDBGRQ can be deasserted. It is also used for other purposes in the ETM, and care must be taken to ensure the timing of this signal is appropriate because it does not come through the main core/ETM interface.


Invasive debug enable.

At logic 1, indicates that invasive debug is enabled.


Coprocessor interface address.

The relevant fields of the MRC or MCR instruction are encoded here as follows:

Bits 14:12 <Opcode_1>

Bits 11:8 <CRn>

Bits 7:4 <CRm>

Bit 3 = 0 cp14

Bit 3 = 1 cp15

Bits 2:0 <Opcode_2>.


Coprocessor interface commit

If this signal is LOW two cycles after ETMCPENABLE is asserted, the transfer is canceled and must not take any effect.


Coprocessor interface enable

ETMCPWRITE and ETMCPADDRESS are valid this cycle, and the remaining signals are valid two cycles later.

ETMCPSECCTL[1:0]InputCoprocessor interface security controlCLKVCORE
ETMCPWDATA[31:0]InputCoprocessor interface write value.CLKVCORE

Coprocessor interface read or write.

This signal is asserted for writes.

ETMDA[31:3]InputAddress for data transfer.CLKVCORE
ETMDACTL[17:0]InputData address interface control signals.CLKVCORE
ETMDBGRQOutputRequest from the CoreSight ETM11 for the core to enter debug state. This must be ORed with any ASIC-level DBGRQ signals before being connected to the core EDBGRQ input.CLKVCORE
ETMDD[63:0]InputContains the data value for a Load, Store, MRC, or MCR instruction.CLKVCORE
ETMDDCTL[3:0]InputData interface control signals.CLKVCORE
ETMDD2[63:0]InputContains the data value for a Store or MCR instruction. Only for use with an MPCore processor.CLKVCORE
ETMDDCTL2[1:0]InputData interface control signals. Only for use with an ARM11 MPCore processor.CLKVCORE

When HIGH, the ATB interface is enabled.

When LOW, logic related to the to the ATB interface can be clock-gated.

ETMIA[31:0]InputAddress for executed instruction.CLKVCORE
ETMIACTL[17:0]InputInstruction address interface control signals.CLKVCORE
ETMIARET[31:0]InputAddress to return to if branch is incorrectly predicted.CLKVCORE
ETMIASECCTL[1:0]InputInstruction interface security control signals.CLKVCORE
ETMPADV[2:0]InputPipeline advance signals.CLKVCORE

When HIGH, indicates that CoreSight ETM11 is in use.

When LOW:

  • external logic supporting CoreSight ETM11 can be clock-gated to conserve power

  • the ARM11 processor disables the CoreSight ETM11 interface

  • logic within CoreSight ETM11 is clock-gated to conserve power.

ETMWFIPENDINGInputIndicates that the ARM11 processor is about to go into Standby mode, and that the ETM must drain its FIFO.CLKVCORE
ETPSUPInputIndicates a trace port is connected.-VCORE
EVNTBUS[19:0]InputGives the status of the performance monitoring events. Used as extended external inputs. Not used on ARM11 MPCore processor.CLKVCORE
EXTIN[3:0]InputExternal input resources.See footnote [1]VCORE

Acknowledge signal for the EXTIN[3:0] bus.

When EXTSBYPASS is HIGH, EXTINACK[3:0] are not valid and can be ignored.

EXTOUT[1:0]OutputExternal outputs.See footnote aVCORE

Acknowledge signals for the EXTOUT[1:0] bus.

When EXTSBYPASS is HIGH, these signals must be tied LOW.


EXTSBYPASS is a single bit input to the ETM that is used to bypass the synchronization of the external inputs EXTIN[3:0] and external outputs EXTOUT[1:0].


  • a HIGH output on any bit of EXTOUT[1:0] is held until the corresponding bit of EXTOUTACK[1:0] is asserted HIGH

  • a HIGH on any bit of EXTIN[3:0] must remain held until the ETM asserts the corresponding bit of EXTINACK[3:0] HIGH.

When EXTSBYPASS is HIGH, EXTOUT[1:0] outputs are valid on the rising edge of CLK and EXTIN[3:0] inputs must be valid on the rising edge of CLK.


For validation purposes only.

Indicates when various events occur before being written to the FIFO.

MAXCORES[2:0]InputWhere an ETM is shared between multiple cores, this signal specifies the number of cores the ETM can trace. It must be tied to the number of cores sharing the ETM minus 1.-VCORE
MAXEXTIN[2:0]InputExternal inputs supported by the ASIC (maximum 4). This appears in the configuration code register.-VCORE
MAXEXTOUT[1:0]InputExternal outputs supported by the ASIC (maximum 2). This appears in the configuration code register.-VCORE
MAXPORTSIZE[3:0]InputMaximum port size supported. See MAXPORTSIZE in ETM11CS and ETM11CSSingle.-VCORE

Indicates power down of the Core domain.

Active LOW.

nETMWFIREADYOutputIndicates that CoreSight ETM11 FIFO is empty and that the ARM11 processor can be put into Standby mode.CLKVCORE
NIDENInputNon-invasive debug enable.-VSOC

Main reset.

Resets all registers in the CLK domain

Internally synchronizedVSOC

Indicates power down of the SoC domain.

Active LOW.

PADDRDBG[11:2]InputDebug APB Address Bus.PCLKDBGVSOC

Originates as an output signal from either the ETMJTAGPORT or Debug Access Port (DAP):

  • PADDRDBG31 at logic 1 indicates an access from hardware (JTAG)

  • PADDRDBG31 at logic 0 indicates an access from software.

PCLKDBGInputDebug APB clock.-VSOC
PENABLEDBGInputThe Debug APB interface is enabled for a transfer.PCLKDBGVSOC

Currently requested port mode.

Not used in a CoreSight system.


Currently requested port size.

Not used in a CoreSight system.

PRDATADBG[31:0]OutputDebug APB read data.PCLKDBGVSOC
PREADYDBGOutputUsed to extend Debug APB transfers.PCLKDBGVSOC
PRESETDBGnInputDebug APB interface reset. Internally synchronizedVSOC
PSELDBGInputDebug APB Slave select signal.PCLKDBGVSOC
PWDATADBG[31:0]InputDebug APB write data.PCLKDBGVSOC
PWRITEDBGInputDebug APB transfer direction (!Read/Write).PCLKDBGVSOC
RSTBYPASSInputReset synchronization bypass.-VSOC
SEInputScan enable.-VSOC
THUMB2ENInputIndicates a Thumb-2 enabled core.CLKVCORE
TRIGOUTOutputTrigger request status signal.See footnote [2]VSOC
TRIGOUTACKInputATB trigger acknowledge.-VSOC
TRIGSBYPASSInputTrigger synchronization bypass.-VSOC
TRUSTZONEENInputIndicates a TrustZone enabled core.CLKVCORE

[1] If EXTSBYPASS is 1, then EXTIN[3:0] must be generated on CLK and EXTOUT[1:0] must be sampled on CLK. If EXTSBYPASS is 0, then there is no such restriction. See CoreSight ETM11 Integration Manual for further details.

[2] If TRIGSBYPASS is 1, then TRIGOUT must be sampled on ATCLK. If TRIGSBYPASS is 0, then there is no such restriction.

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