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Appendix B. Revisions

This appendix describes the technical changes between released issues of this book.

Table B.1. Differences between issue F and issue G

Added the DDR PHY Interface (DFI) pad interface feature including the DFI signals and registers

Throughout book


Updated description of the supported memory data bus widthsSupported memory widthsAll revisions
Removed support for 64-bit SDRAMsTable 1.1r4p0
Updated AXI slave interface attributes and added read interleave depthAXI slave interface attributesAll revisions

Updated bus widths for arprot, awprot, arcache, and awcache

All revisions

Added user_config1 signals and user_config1 Register


Added configurable bus width for the user_status, user_config, and user_config1 signalsThroughout book


Added configurable bus width for the arid, awid, bid, rid, and wid signalsThroughout book


Added early write response featureEarly BRESP


Added Read After Write hazardHazard detection


Updated description of system state 11Table 2.6All revisions
Updated listing of the dynamic low-power modes operation and removed the illegal bit combinationsTable 2.7All revisions

Removed restriction of issuing the NOP command when the controller includes the NVM plug-in


Support for moving all of the memory devices to the deep power-down modeDeep Power-Downr4p0
Added a new section TrustZone Support for DMCTrustZone technology supportr4p0
Added supported bit, or field, values to the timing registersChapter 3 Programmers ModelAll revisions
Updated the function description for fp_time bitTable 3.7r4p0

Field names changed as follows:

  • from memory_banks[1:0] to banks_bit[1:0]

  • from memory_type to memory_support

  • from memory_width to max_memory_width

Memory Controller Status Register

Added the combined SDR-DDR-LPDDR option to the memory_support fieldr2p0
Updated description of the max_memory_width fieldAll revisions
Updated description of the sr_enable, fp_time, and fp_enable bitsMemory Configuration RegisterAll revisions
Removed restriction of enabling the sr_enable and stop_mem_clock bits at the same timer4p0
Updated description of the cas_half_cycle bitCAS Latency RegisterAll revisions
Updated description of the memory_width fieldMemory Configuration 2 Registerr2p0
memory_type field name changed to memory_protocol
Added the combined SDR-DDR-LPDDR option to the memory_protocol field
a_gt_m_sync bit and sync bit changed to clock_cfg field
Updated description of the memory_cfg3 RegisterMemory Configuration 3 Registerr2p0
Added the read_transfer_delay RegisterRead Transfer Delay Registerr4p0
brc_n_rbc field name changed to address_fmtChip Configuration Registerr3p0
Added the feature_ctrl RegisterFeature Control Registerr4p0
Updated the most significant byte of the conceptual peripheral ID registerAll revisions
Added requirement to set cactive and csysack HIGH when the controller exits integration test modeIntegration Configuration RegisterAll revisions
Updated register description and added an _int suffix to each bit nameIntegration Outputs RegisterAll revisions
Replaced the old Device Driver section with new contentChapter 5 Device Driverr4p0
Updated description of the tie-off signalsTie-offsAll revisions
Added note about using EBI when DFI is implementedEBI signalsr4p0

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