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4.1. Integration test registers

Test registers are provided for integration testing.

Figure 4.1 shows the integration test register map.

Figure 4.1. Integration test register map

Figure 4.1. Integration test register map

Table 4.1 shows the integration test registers in base offset order.

Table 4.1. DMC test Register summary
0xE00int_cfgRW0x0Integration Configuration Register
0xE04int_inputsRO-[a]Integration Inputs Register
0xE08int_outputsWO-Integration Outputs Register

[a] Dependent on the tie-off signals.

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